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soc/intel: Move pch_enable_ioapic() to common code 

List of changes:
1. Move pch_enable_ioapic() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.

TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.

Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-09-29 13:55:50 +05:30
parent 18b1984f86
commit 1366e4438d
9 changed files with 35 additions and 161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/soc/intel/cannonlake/lpc.c
View File

@ -90,28 +90,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
static void pch_enable_ioapic(const struct device *dev)
{
u32 reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@ -207,7 +185,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */
pch_enable_ioapic(dev);
pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);

2
src/soc/intel/common/block/include/intelblocks/lpc_lib.h
View File

@ -107,5 +107,7 @@ void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
/* Add resource into LPC PCI device space */
void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
uintptr_t base, size_t size, unsigned long flags);
/* Enable PCH IOAPIC */
void pch_enable_ioapic(void);
#endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */

25
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -2,6 +2,7 @@
#define __SIMPLE_DEVICE__
#include <arch/ioapic.h>
#include <assert.h>
#include <console/console.h>
#include <device/pci.h>
@ -292,3 +293,27 @@ void lpc_disable_clkrun(void)
const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL);
pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);
}
/* Enable PCH IOAPIC */
void pch_enable_ioapic(void)
{
uint32_t reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}

24
src/soc/intel/elkhartlake/espi.c
View File

@ -64,28 +64,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
static void pch_enable_ioapic(const struct device *dev)
{
uint32_t reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@ -182,7 +160,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */
pch_enable_ioapic(dev);
pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);

24
src/soc/intel/icelake/espi.c
View File

@ -83,28 +83,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
static void pch_enable_ioapic(const struct device *dev)
{
u32 reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@ -201,7 +179,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */
pch_enable_ioapic(dev);
pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);

24
src/soc/intel/jasperlake/espi.c
View File

@ -65,28 +65,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
static void pch_enable_ioapic(const struct device *dev)
{
u32 reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@ -183,7 +161,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */
pch_enable_ioapic(dev);
pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);

25
src/soc/intel/skylake/lpc.c
View File

@ -29,29 +29,6 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
return skl_lpc_fixed_mmio_ranges;
}
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
{
const config_t *config = config_of(dev);
@ -96,7 +73,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */
pch_enable_ioapic(dev);
pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);

24
src/soc/intel/tigerlake/espi.c
View File

@ -71,28 +71,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
static void pch_enable_ioapic(const struct device *dev)
{
u32 reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@ -189,7 +167,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */
pch_enable_ioapic(dev);
pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);

24
src/soc/intel/xeon_sp/cpx/chip.c
View File

@ -6,6 +6,7 @@
#include <cpu/x86/lapic.h>
#include <device/pci.h>
#include <fsp/api.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <post.h>
#include <soc/acpi.h>
@ -557,27 +558,6 @@ static void attach_iio_stacks(struct device *dev)
DEV_FUNC_EXIT(dev);
}
static void pch_enable_ioapic(const struct device *dev)
{
uint32_t reg32;
set_ioapic_id((void *)IO_APIC_ADDR, 2);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 1);
reg32 &= ~0x00ff0000;
reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 1, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write((void *)IO_APIC_ADDR, 3, 1);
}
struct pci_operations soc_pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
@ -604,7 +584,7 @@ static void chip_init(void *data)
{
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
fsp_silicon_init(false);
pch_enable_ioapic(NULL);
pch_enable_ioapic();
setup_lapic();
p2sb_unhide();
}