From 13818f5c5cd55ce8bfa3c5942978a07c2d80f5eb Mon Sep 17 00:00:00 2001
From: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Date: Wed, 24 Feb 2021 17:45:07 +0800
Subject: [PATCH] mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz

Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42

Change to:
.rise_time_ns = 110
.fall_time_ns = 34

BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
---
 src/mainboard/google/zork/variants/shuboz/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb
index 436f0edc9a..16c18b5117 100644
--- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb
@@ -35,8 +35,8 @@ chip soc/amd/picasso
 
 	register "i2c[3]" = "{
 		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */
-		.fall_time_ns = 42,  /* 1.26v to 0 */
+		.rise_time_ns = 110, /* 0 to 1.26v (1.8 * .7) */
+		.fall_time_ns = 34,  /* 1.26v to 0 */
 		.early_init = true,
 	}"