drivers/intel/fsp1_1: Configure UART after memory init
FSP code will default enable the onboard serial port. When external serial port is used, this onboard port needs to be disabled. Add function mainboard_after_memory_init() function to perform required actions to re-enabled output to external serial port. BUG=N/A TEST=LPC Post card on Intel Cherry Hill Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2016 Intel Corporation
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* Copyright (C) 2018 Eltan B.V.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -91,5 +92,6 @@ void soc_pre_ram_init(struct romstage_params *params);
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/* Update the SOC specific memory config param for mma. */
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void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
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struct mma_config_param *mma_cfg);
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void mainboard_after_memory_init(void);
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#endif /* _COMMON_ROMSTAGE_H_ */
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@ -125,6 +125,7 @@ void raminit(struct romstage_params *params)
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timestamp_add_now(TS_FSP_MEMORY_INIT_START);
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post_code(POST_FSP_MEMORY_INIT);
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status = fsp_memory_init(&fsp_memory_init_params);
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mainboard_after_memory_init();
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post_code(0x37);
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timestamp_add_now(TS_FSP_MEMORY_INIT_END);
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@ -322,3 +323,9 @@ __weak void soc_memory_init_params(
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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/* Initialize the SoC after MemoryInit */
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__weak void mainboard_after_memory_init(void)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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