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Use symbolic names for some MTRR bits instead of numbers in CAR code 

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2011-04-14 20:06:30 +00:00 committed by Stefan Reinauer
parent 528b43db32
commit 139e6f9555
4 changed files with 16 additions and 16 deletions
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4
src/cpu/amd/car/cache_as_ram.inc
View File

@ -77,7 +77,7 @@ cache_as_ram_setup:
/* Check if cpu_init_detected. */ /* Check if cpu_init_detected. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
andl $(1 << 11), %eax andl $MTRRdefTypeEn, %eax
movl %eax, %ebx /* We store the status. */ movl %eax, %ebx /* We store the status. */
jmp_if_k8(CAR_FAM10_out_post_errata) jmp_if_k8(CAR_FAM10_out_post_errata)
@ -306,7 +306,7 @@ clear_fixed_var_mtrr_out:
jmp_if_k8(wbcache_post_fam10_setup) jmp_if_k8(wbcache_post_fam10_setup)
movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
wbcache_post_fam10_setup: wbcache_post_fam10_setup:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */

4
src/cpu/intel/car/cache_as_ram.inc
View File

@ -254,7 +254,7 @@ clear_fixed_var_mtrr_out:
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
@ -354,7 +354,7 @@ lout:
*/ */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */
wrmsr wrmsr
/* Enable cache. */ /* Enable cache. */

12
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -63,14 +63,14 @@ clear_mtrrs:
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx movl $(MTRRphysMask_MSR(0)), %ecx
movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx movl $0x0000000f, %edx
wrmsr wrmsr
/* Enable MTRR. */ /* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
orl $(1 << 11), %eax orl $MTRRdefTypeEn, %eax
wrmsr wrmsr
/* Enable L2 cache. */ /* Enable L2 cache. */
@ -118,7 +118,7 @@ clear_mtrrs:
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
@ -160,7 +160,7 @@ clear_mtrrs:
/* Disable MTRR. */ /* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
andl $(~(1 << 11)), %eax andl $(~MTRRdefTypeEn), %eax
wrmsr wrmsr
post_code(0x31) post_code(0x31)
@ -201,7 +201,7 @@ clear_mtrrs:
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
movl $MTRRphysMask_MSR(0), %ecx movl $MTRRphysMask_MSR(0), %ecx
movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx // 36bit address space movl $0x0000000f, %edx // 36bit address space
wrmsr wrmsr
@ -217,7 +217,7 @@ clear_mtrrs:
/* Enable MTRR. */ /* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
orl $(1 << 11), %eax orl $MTRRdefTypeEn, %eax
wrmsr wrmsr
post_code(0x3b) post_code(0x3b)

12
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -70,14 +70,14 @@ clear_mtrrs:
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx movl $(MTRRphysMask_MSR(0)), %ecx
movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx movl $0x0000000f, %edx
wrmsr wrmsr
/* Enable MTRR. */ /* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
orl $(1 << 11), %eax orl $MTRRdefTypeEn, %eax
wrmsr wrmsr
/* Enable L2 cache. */ /* Enable L2 cache. */
@ -125,7 +125,7 @@ clear_mtrrs:
movl $MTRRphysMask_MSR(1), %ecx movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
@ -167,7 +167,7 @@ clear_mtrrs:
/* Disable MTRR. */ /* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
andl $(~(1 << 11)), %eax andl $(~MTRRdefTypeEn), %eax
wrmsr wrmsr
post_code(0x31) post_code(0x31)
@ -208,7 +208,7 @@ clear_mtrrs:
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
movl $MTRRphysMask_MSR(0), %ecx movl $MTRRphysMask_MSR(0), %ecx
movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx // 36bit address space movl $0x0000000f, %edx // 36bit address space
wrmsr wrmsr
@ -224,7 +224,7 @@ clear_mtrrs:
/* Enable MTRR. */ /* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
rdmsr rdmsr
orl $(1 << 11), %eax orl $MTRRdefTypeEn, %eax
wrmsr wrmsr
post_code(0x3b) post_code(0x3b)