cpu/intel/common: rework AES-NI locking

Simplify the AES-NI code by using msr_set and correct the comment.

Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/intel/common/common.h

@@ -28,8 +28,8 @@ bool intel_ht_supported(void);
 bool intel_ht_sibling(void);
 
 /*
- * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling
+ * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended changes
- * as suggested in Intel document 325384-070US.
+ * to the enablement state as suggested in Intel document 325384-070US.
  */
 void set_aesni_lock(void);
 

src/cpu/intel/common/common_init.c

@@ -266,10 +266,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
 	}
 }
 
-/*
- * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling
- * as suggested in Intel document 325384-070US.
- */
 void set_aesni_lock(void)
 {
 	msr_t msr;
@@ -279,8 +275,8 @@ void set_aesni_lock(void)
 		return;
 
 	msr = rdmsr(MSR_FEATURE_CONFIG);
-	if ((msr.lo & 1) == 0) {
+	if (msr.lo & AESNI_LOCK)
-		msr.lo |= 1;
+		return;
-		wrmsr(MSR_FEATURE_CONFIG, msr);
+
-	}
+	msr_set(MSR_FEATURE_CONFIG, AESNI_LOCK);
 }

src/include/cpu/intel/msr.h

@@ -6,6 +6,6 @@
  */
 
 #define MSR_FEATURE_CONFIG	0x13c
-#define  AESNI_LOCK_BIT		0
+#define  AESNI_LOCK		(1 << 0)
 
 #endif /* CPU_INTEL_MSR_H */