diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 842e977d3e..c3e716527a 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include "ipmi.h" diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index bacbd6fffa..4124f420c2 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -2,13 +2,13 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) -subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx -subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx +subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg +subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg -bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c -romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c +bootblock-y += bootblock.c spi.c lpc.c pch.c +romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c romstage-y += ../../../cpu/intel/car/romstage.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c ramstage.c chip_common.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += nb_acpi.c acpi.c diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 4b15435619..15bd5dec0e 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/xeon_sp/include/soc/gpio.h b/src/soc/intel/xeon_sp/include/soc/gpio.h index 04eb9ae31c..e7ffa6ffcd 100644 --- a/src/soc/intel/xeon_sp/include/soc/gpio.h +++ b/src/soc/intel/xeon_sp/include/soc/gpio.h @@ -3,7 +3,7 @@ #ifndef _SOC_GPIO_H_ #define _SOC_GPIO_H_ -#include +#include #include /* diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h index 156a22a2ba..0be14ae966 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch.h +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -10,6 +10,5 @@ void pch_disable_devfn(struct device *dev); #endif void override_hpet_ioapic_bdf(void); -void pch_lock_dmictl(void); #endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/lbg/Makefile.inc b/src/soc/intel/xeon_sp/lbg/Makefile.inc new file mode 100644 index 0000000000..d3dd76009b --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += soc_pch.c soc_gpio.c +romstage-y += soc_pmutil.c soc_gpio.c +ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/lbg/include diff --git a/src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h b/src/soc/intel/xeon_sp/lbg/include/soc/gpio_soc_defs.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h rename to src/soc/intel/xeon_sp/lbg/include/soc/gpio_soc_defs.h diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h similarity index 100% rename from src/soc/intel/xeon_sp/include/soc/pcr_ids.h rename to src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h new file mode 100644 index 0000000000..2d87be34ec --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_SOC_PCH_H_ +#define _SOC_SOC_PCH_H_ + +void pch_lock_dmictl(void); + +#endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/gpio.c b/src/soc/intel/xeon_sp/lbg/soc_gpio.c similarity index 100% rename from src/soc/intel/xeon_sp/gpio.c rename to src/soc/intel/xeon_sp/lbg/soc_gpio.c diff --git a/src/soc/intel/xeon_sp/lbg/soc_pch.c b/src/soc/intel/xeon_sp/lbg/soc_pch.c new file mode 100644 index 0000000000..83ed20a5d2 --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/soc_pch.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); + printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; + pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT + */ + soc_config_acpibase(); +} + +void pch_lock_dmictl(void) +{ + uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); +} diff --git a/src/soc/intel/xeon_sp/lbg/soc_pmutil.c b/src/soc/intel/xeon_sp/lbg/soc_pmutil.c new file mode 100644 index 0000000000..2fbb9ff012 --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/soc_pmutil.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include + +uint8_t *pmc_mmio_regs(void) +{ + return (void *)(uintptr_t) pci_read_config32(PCH_DEV_PMC, PWRMBASE); +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t) (pmc_mmio_regs()); +} + +uint32_t *soc_pmc_etr_addr(void) +{ + /* + * The pointer returned must not be cached, because the address depends on the + * MMCONF base address and the assigned PCI bus number, which both may change + * during the boot process! + */ + return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); +} + +int soc_get_rtc_failed(void) +{ + uint32_t pmcon_b = pci_s_read_config32(PCH_DEV_PMC, GEN_PMCON_B); + int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD); + + if (rtc_fail) + printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__); + + return rtc_fail; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint8_t *pmc; + + ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); + ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); + + pmc = pmc_mmio_regs(); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); +} + +/* + * Set which power state system will be after reapplying + * the power (from G3 State) + */ +void pmc_soc_set_afterg3_en(const bool on) +{ + uint8_t reg8; + + reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B); + if (on) + reg8 &= ~SLEEP_AFTER_POWER_FAIL; + else + reg8 |= SLEEP_AFTER_POWER_FAIL; + pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); +} diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index a8f47d3378..23af6d9cb1 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -11,46 +11,6 @@ #include #include -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_DMICTL 0x2234 -#define PCR_DMI_DMICTL_SRLOCK (1 << 31) -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 - -static void soc_config_acpibase(void) -{ - uint32_t reg32; - - /* Disable ABASE in PMC Device first before changing Base Address */ - reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); - - /* Program ACPI Base */ - pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); - - /* Enable ACPI in PMC */ - pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); - - uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); - printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); - /* - * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] - * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] - */ - reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; - pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); - pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); -} - -void bootblock_pch_init(void) -{ - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT - */ - soc_config_acpibase(); -} - void override_hpet_ioapic_bdf(void) { union p2sb_bdf ioapic_bdf = { @@ -67,9 +27,3 @@ void override_hpet_ioapic_bdf(void) p2sb_set_ioapic_bdf(ioapic_bdf); p2sb_set_hpet_bdf(hpet_bdf); } - -void pch_lock_dmictl(void) -{ - uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); -} diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index 3ac5d46243..336e867a96 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -90,42 +90,11 @@ const char *const *soc_std_gpe_sts_array(size_t *gpe_arr) return gpe_sts_bits; } -uint8_t *pmc_mmio_regs(void) -{ - return (void *)(uintptr_t)pci_read_config32(PCH_DEV_PMC, PWRMBASE); -} - -uintptr_t soc_read_pmc_base(void) -{ - return (uintptr_t)(pmc_mmio_regs()); -} - -uint32_t *soc_pmc_etr_addr(void) -{ - /* - * The pointer returned must not be cached, because the address depends on the - * MMCONF base address and the assigned PCI bus number, which both may change - * during the boot process! - */ - return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); -} - void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { /* No functionality for this yet */ } -int soc_get_rtc_failed(void) -{ - uint32_t pmcon_b = pci_s_read_config32(PCH_DEV_PMC, GEN_PMCON_B); - int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD); - - if (rtc_fail) - printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__); - - return rtc_fail; -} - /* Return 0, 3, or 5 to indicate the previous sleep state. */ int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { @@ -141,41 +110,8 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_st return prev_sleep_state; } -void soc_fill_power_state(struct chipset_power_state *ps) -{ - uint8_t *pmc; - - ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); - ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); - - pmc = pmc_mmio_regs(); - ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); - ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); - - printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); - - printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", - ps->gblrst_cause[0], ps->gblrst_cause[1]); -} - /* STM Support */ uint16_t get_pmbase(void) { return ACPI_BASE_ADDRESS; } - -/* - * Set which power state system will be after reapplying - * the power (from G3 State) - */ -void pmc_soc_set_afterg3_en(const bool on) -{ - uint8_t reg8; - reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B); - if (on) - reg8 &= ~SLEEP_AFTER_POWER_FAIL; - else - reg8 |= SLEEP_AFTER_POWER_FAIL; - pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); -} diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 78507879d1..efdeef8ee3 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include