diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 6f227407de..822ee780ec 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -96,7 +96,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->PcdEnableHsuart0 = config->PcdEnableHsuart0;
 	params->PcdEnableHsuart1 = config->PcdEnableHsuart1;
 	params->PcdEnableAzalia = config->PcdEnableAzalia;
-	params->AzaliaConfigPtr = config->AzaliaConfigPtr;
 	params->PcdEnableSata = config->PcdEnableSata;
 	params->PcdEnableXhci = config->PcdEnableXhci;
 	params->PcdEnableLpe = config->PcdEnableLpe;
@@ -109,7 +108,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->PcdEnableI2C4 = config->PcdEnableI2C4;
 	params->PcdEnableI2C5 = config->PcdEnableI2C5;
 	params->PcdEnableI2C6 = config->PcdEnableI2C6;
-	params->PcdGraphicsConfigPtr = config->PcdGraphicsConfigPtr;
+	params->GraphicsConfigPtr = 0;
+	params->AzaliaConfigPtr = 0;
 	params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
 	params->ChvSvidConfig = config->ChvSvidConfig;
 	params->DptfDisable = config->DptfDisable;
@@ -171,11 +171,9 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 		new->PcdEnableHsuart1);
 	soc_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia,
 		new->PcdEnableAzalia);
-	soc_display_upd_value("AzaliaVerbTablePtr", 4,
-		(uint32_t)old->AzaliaVerbTablePtr,
-		(uint32_t)new->AzaliaVerbTablePtr);
-	soc_display_upd_value("AzaliaConfigPtr", 4, old->AzaliaConfigPtr,
-		new->AzaliaConfigPtr);
+	soc_display_upd_value("AzaliaConfigPtr", 4,
+			(uint32_t)old->AzaliaConfigPtr,
+			(uint32_t)new->AzaliaConfigPtr);
 	soc_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata,
 		new->PcdEnableSata);
 	soc_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci,
@@ -201,7 +199,7 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	soc_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6,
 		new->PcdEnableI2C6);
 	soc_display_upd_value("PcdGraphicsConfigPtr", 4,
-		old->PcdGraphicsConfigPtr, new->PcdGraphicsConfigPtr);
+		old->GraphicsConfigPtr, new->GraphicsConfigPtr);
 	soc_display_upd_value("GpioFamilyInitTablePtr", 4,
 		(uint32_t)old->GpioFamilyInitTablePtr,
 		(uint32_t)new->GpioFamilyInitTablePtr);
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index ff68014d9c..e415dfd78b 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -85,7 +85,6 @@ struct soc_intel_braswell_config {
 	UINT8  PcdEnableHsuart0;
 	UINT8  PcdEnableHsuart1;
 	UINT8  PcdEnableAzalia;
-	UINT32 AzaliaConfigPtr;
 	UINT8  PcdEnableSata;
 	UINT8  PcdEnableXhci;
 	UINT8  PcdEnableLpe;
@@ -98,7 +97,6 @@ struct soc_intel_braswell_config {
 	UINT8  PcdEnableI2C4;
 	UINT8  PcdEnableI2C5;
 	UINT8  PcdEnableI2C6;
-	UINT32 PcdGraphicsConfigPtr;
 	UINT8  PunitPwrConfigDisable;
 	UINT8  ChvSvidConfig;
 	UINT8  DptfDisable;
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index b12ec04712..3aba7c7c5d 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -47,5 +47,5 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
 		} else
 			vbt_data = NULL;
 	}
-	params->PcdGraphicsConfigPtr = (u32)vbt_data;
+	params->GraphicsConfigPtr = (u32)vbt_data;
 }