soc/intel/skylake: Enable Energy/Performance Bias control

Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on
Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so
do it there too.

Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matthew Garrett 2019-07-19 17:02:07 -07:00 committed by Martin Roth
parent bcbc514cfa
commit 13e7a2fd35
1 changed files with 1 additions and 0 deletions

View File

@ -313,6 +313,7 @@ static void configure_misc(void)
msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/
msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */
msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */
msr.lo |= (1 << 23); /* Lock it */
wrmsr(MSR_POWER_CTL, msr);