soc/intel/cannonlake: Allow coreboot to handle SPI lockdown
This patch disables FSP-S SPI lockdown UPDs and lets coreboot perform SPI lockdown (i.e.flash register DLOCK, FLOCKDN, and WRSDIS before end of post) in ramstage. BUG=b:138200201 TEST=FSP debug build suggests those UPDs are disable now. Change-Id: Id7a6b9859e058b9f1ec1bd45d2c388c02b8ac18c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
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@ -421,31 +421,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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tconfig->PchLockDownBiosInterface = 0;
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params->PchLockDownBiosLock = 0;
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params->PchLockDownRtcMemoryLock = 0;
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#if CONFIG(SOC_INTEL_COMETLAKE)
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/*
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* TODO: Disable SpiFlashCfgLockDown config after FSP provides
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* dedicated UPD
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*
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* Skip SPI Flash Lockdown from inside FSP.
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* Making this config "0" means FSP won't set the FLOCKDN bit
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* of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL).
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* So, it becomes coreboot's responsibility to set this bit
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* before end of POST for security concerns.
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*/
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// params->SpiFlashCfgLockDown = 0;
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params->SpiFlashCfgLockDown = 0;
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#endif
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} else {
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tconfig->PchLockDownGlobalSmi = 1;
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tconfig->PchLockDownBiosInterface = 1;
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params->PchLockDownBiosLock = 1;
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params->PchLockDownRtcMemoryLock = 1;
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#if CONFIG(SOC_INTEL_COMETLAKE)
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/*
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* TODO: Enable SpiFlashCfgLockDown config after FSP provides
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* dedicated UPD
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*
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* Enable SPI Flash Lockdown from inside FSP.
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* Making this config "1" means FSP will set the FLOCKDN bit
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* of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL).
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*/
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// params->SpiFlashCfgLockDown = 1;
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params->SpiFlashCfgLockDown = 1;
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#endif
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}
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}
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