lynxpoint: Add ACPI Method to enable GPIO as wake source
This is an LPT-LP specific method that will enable a specific GPIO as an ACPI SCI wake source. It can be used by a device _DSW method to enable a pin that is otherwise not configured to generate SCI at runtime. It will set: - GPIO owner to ACPI - GPIO route to SCI - GPIO config to GPIO, Input, Inverted Also clean up and remove ACPI field definitions that are unused and/or incorrect. Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56621 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4189 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie
Stefan Reinauer
parent
96f77bd0d9
commit
14031db21f
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@ -32,6 +32,8 @@ Device (LPCB)
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DIDH, 8, // Device ID High Byte
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Offset (0x40),
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PMBS, 16, // PMBASE
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Offset (0x48),
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GPBS, 16, // GPIOBASE
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Offset (0x60), // Interrupt Routing Registers
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PRTA, 8,
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PRTB, 8,
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@ -47,24 +49,6 @@ Device (LPCB)
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IOD0, 8,
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IOD1, 8,
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Offset (0xb8), // GPIO Routing Control
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GR00, 2,
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GR01, 2,
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GR02, 2,
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GR03, 2,
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GR04, 2,
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GR05, 2,
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GR06, 2,
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GR07, 2,
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GR08, 2,
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GR09, 2,
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GR10, 2,
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GR11, 2,
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GR12, 2,
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GR13, 2,
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GR14, 2,
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GR15, 2,
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Offset (0xf0), // RCBA
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RCEN, 1,
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, 13,
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@ -0,0 +1,94 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/* LynxPoint-H */
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Scope (\_SB.PCI0.LPCB)
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{
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// GWAK: Setup GPIO as ACPI GPE for Wake
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// Arg0: GPIO Number
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Method (GWAK, 1, NotSerialized)
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{
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// Local0 = GPIO Base Address
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Store (And (GPBS, Not(0x1)), Local0)
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// Local1 = BANK, Local2 = OFFSET
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Divide (Arg0, 32, Local2, Local1)
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//
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// Set OWNER to ACPI
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//
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// Local3 = GPIOBASE + GPIO_OWN(BANK)
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Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
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// GPIO_OWN(BANK)
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OperationRegion (IOWN, SystemIO, Local3, 4)
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Field (IOWN, AnyAcc, NoLock, Preserve) {
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GOWN, 32,
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}
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// GPIO_OWN[GPIO] = 0 (ACPI)
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Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
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//
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// Set ROUTE to SCI
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//
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// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
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Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
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// GPIO_ROUTE(BANK)
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OperationRegion (IROU, SystemIO, Local3, 4)
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Field (IROU, AnyAcc, NoLock, Preserve) {
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GROU, 32,
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}
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// GPIO_ROUTE[GPIO] = 0 (SCI)
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Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
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//
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// Set GPnCONFIG to GPIO|INPUT|INVERT
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//
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// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
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Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
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// GPnCONFIG(GPIO)
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OperationRegion (GPNC, SystemIO, Local3, 8)
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Field (GPNC, AnyAcc, NoLock, Preserve) {
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GMOD, 1, // MODE: 0=NATIVE 1=GPIO
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, 1,
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GIOS, 1, // IO_SEL: 0=OUTPUT 1=INPUT
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GINV, 1, // INVERT: 0=NORMAL 1=INVERT
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GLES, 1, // LxEB: 0=EDGE 1=LEVEL
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, 24,
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ILVL, 1, // INPUT: 0=LOW 1=HIGH
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OLVL, 1, // OUTPUT: 0=LOW 1=HIGH
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GPWP, 2, // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
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ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE
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}
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Store (0x1, GMOD) // GPIO
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Store (0x1, GIOS) // INPUT
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Store (0x1, GINV) // INVERT
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}
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}
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@ -42,173 +42,6 @@ Scope(\)
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TRP0, 8 // IO-Trap at 0x808
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}
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// PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
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OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0xff)
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Field(PMIO, ByteAcc, NoLock, Preserve)
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{
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Offset(0x20), // GPE0_STS
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, 16,
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GS00, 1, // GPIO00 SCI/Wake Status
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GS01, 1, // GPIO01 SCI/Wake Status
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GS02, 1, // GPIO02 SCI/Wake Status
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GS03, 1, // GPIO03 SCI/Wake Status
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GS04, 1, // GPIO04 SCI/Wake Status
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GS05, 1, // GPIO05 SCI/Wake Status
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GS06, 1, // GPIO06 SCI/Wake Status
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GS07, 1, // GPIO07 SCI/Wake Status
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GS08, 1, // GPIO08 SCI/Wake Status
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GS09, 1, // GPIO09 SCI/Wake Status
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GS10, 1, // GPIO10 SCI/Wake Status
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GS11, 1, // GPIO11 SCI/Wake Status
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GS12, 1, // GPIO12 SCI/Wake Status
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GS13, 1, // GPIO13 SCI/Wake Status
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GS14, 1, // GPIO14 SCI/Wake Status
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GS15, 1, // GPIO15 SCI/Wake Status
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Offset(0x28), // GPE0_EN
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, 16,
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GE00, 1, // GPIO00 SCI/Wake Enable
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GE01, 1, // GPIO01 SCI/Wake Enable
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GE02, 1, // GPIO02 SCI/Wake Enable
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GE03, 1, // GPIO03 SCI/Wake Enable
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GE04, 1, // GPIO04 SCI/Wake Enable
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GE05, 1, // GPIO05 SCI/Wake Enable
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GE06, 1, // GPIO06 SCI/Wake Enable
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GE07, 1, // GPIO07 SCI/Wake Enable
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GE08, 1, // GPIO08 SCI/Wake Enable
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GE09, 1, // GPIO09 SCI/Wake Enable
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GE10, 1, // GPIO10 SCI/Wake Enable
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GE11, 1, // GPIO11 SCI/Wake Enable
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GE12, 1, // GPIO12 SCI/Wake Enable
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GE13, 1, // GPIO13 SCI/Wake Enable
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GE14, 1, // GPIO14 SCI/Wake Enable
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GE15, 1, // GPIO15 SCI/Wake Enable
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Offset(0x42), // General Purpose Control
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, 1, // skip 1 bit
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GPEC, 1, // SWGPE_CTRL
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}
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// GPIO IO mapped registers (0x1f.0 reg 0x48.l)
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OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
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Field(GPIO, ByteAcc, NoLock, Preserve)
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{
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Offset(0x00), // GPIO Use Select
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GU00, 8,
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GU01, 8,
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GU02, 8,
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GU03, 8,
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Offset(0x04), // GPIO IO Select
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GIO0, 8,
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GIO1, 8,
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GIO2, 8,
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GIO3, 8,
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Offset(0x0c), // GPIO Level
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GL00, 1,
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GP01, 1,
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GP02, 1,
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GP0e, 1,
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GP04, 1,
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GP05, 1,
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GP06, 1,
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GP07, 1,
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GP08, 1,
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GP09, 1,
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GP10, 1,
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GP11, 1,
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GP12, 1,
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GP13, 1,
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GP14, 1,
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GP15, 1,
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GP16, 1,
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GP17, 1,
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GP18, 1,
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GP19, 1,
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GP20, 1,
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GP21, 1,
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GP22, 1,
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GP23, 1,
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GP24, 1,
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GP25, 1,
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GP26, 1,
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GP27, 1,
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GP28, 1,
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GP29, 1,
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GP30, 1,
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GP31, 1,
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Offset(0x18), // GPIO Blink
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GB00, 8,
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GB01, 8,
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GB02, 8,
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GB03, 8,
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Offset(0x2c), // GPIO Invert
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GIV0, 8,
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GIV1, 8,
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GIV2, 8,
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GIV3, 8,
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Offset(0x30), // GPIO Use Select 2
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GU04, 8,
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GU05, 8,
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GU06, 8,
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GU07, 8,
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Offset(0x34), // GPIO IO Select 2
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GIO4, 8,
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GIO5, 8,
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GIO6, 8,
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GIO7, 8,
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Offset(0x38), // GPIO Level 2
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GP32, 1,
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GP33, 1,
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GP34, 1,
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GP35, 1,
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GP36, 1,
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GP37, 1,
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GP38, 1,
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GP39, 1,
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GP40, 1,
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GP41, 1,
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GP42, 1,
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GP43, 1,
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GP44, 1,
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GP45, 1,
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GP46, 1,
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GP47, 1,
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GP48, 1,
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GP49, 1,
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GP50, 1,
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GP51, 1,
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GP52, 1,
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GP53, 1,
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GP54, 1,
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GP55, 1,
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GP56, 1,
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GP57, 1,
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GP58, 1,
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GP59, 1,
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GP60, 1,
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GP61, 1,
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GP62, 1,
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GP63, 1,
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Offset(0x40), // GPIO Use Select 3
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GU08, 8,
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GU09, 4,
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Offset(0x44), // GPIO IO Select 3
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GIO8, 8,
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GIO9, 4,
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Offset(0x48), // GPIO Level 3
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GP64, 1,
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GP65, 1,
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GP66, 1,
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GP67, 1,
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GP68, 1,
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GP69, 1,
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GP70, 1,
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GP71, 1,
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GP72, 1,
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GP73, 1,
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GP74, 1,
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GP75, 1,
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}
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// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
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OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
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Field(RCRB, DWordAcc, Lock, Preserve)
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@ -270,6 +103,7 @@ Scope(\)
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// Serial IO
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#if CONFIG_INTEL_LYNXPOINT_LP
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#include "serialio.asl"
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#include "lpt_lp.asl"
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#endif
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Method (_OSC, 4)
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