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soc/intel/jasperlake: Add PsysPmax config 

Enable PSYS capability. PSYS is required to safeguard the system
stability if no charger IC.

BUG=b:281479111
TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS

Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196
Reviewed-by: Reka Norman <rekanorman@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chia-Ling Hou 2023-05-15 17:31:57 +08:00 committed by Lean Sheng Tan
parent ede5564b3e
commit 141d0dfafb
2 changed files with 10 additions and 0 deletions
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3
src/soc/intel/jasperlake/chip.h
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@ -419,6 +419,9 @@ struct soc_intel_jasperlake_config {
CD_CLOCK_556_8_MHZ = 7, CD_CLOCK_556_8_MHZ = 7,
} cd_clock; } cd_clock;
/* Platform Power Pmax */
uint16_t PsysPmax;
/* /*
* This is a workaround to mitigate higher SoC power consumption in S0ix * This is a workaround to mitigate higher SoC power consumption in S0ix
* when the CNVI has background activity. * when the CNVI has background activity.

7
src/soc/intel/jasperlake/fsp_params.c
View File

@ -188,6 +188,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
config->PchPmPwrCycDur); config->PchPmPwrCycDur);
/* Set PsysPmax */
if (config->PsysPmax) {
printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
/* PsysPmax is in unit of 1/8 Watt */
params->PsysPmax = config->PsysPmax * 8;
}
/* /*
* Fill Acoustic noise mitigation related configuration * Fill Acoustic noise mitigation related configuration
* JSL only has single VR domain (VCCIN VR), thus filling only index 0 for * JSL only has single VR domain (VCCIN VR), thus filling only index 0 for