arch/x86: Change smm_subregion() prototype

Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/x86/smm/stage_cache.c

@@ -18,14 +18,14 @@
 #include <stage_cache.h>
 #include <types.h>
 
-int __weak smm_subregion(int sub, void **base, size_t *size)
+int __weak smm_subregion(int sub, uintptr_t *base, size_t *size)
 {
 	return -1;
 }
 
 void __weak stage_cache_external_region(void **base, size_t *size)
 {
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+	if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
 		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
 		*base = NULL;
 		*size = 0;

src/drivers/intel/fsp1_1/raminit.c

@@ -53,7 +53,7 @@ void raminit(struct romstage_params *params)
 	UPD_DATA_REGION *upd_ptr;
 	int fsp_verification_failure = 0;
 	EFI_PEI_HOB_POINTERS hob_ptr;
-	char *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
 
 	/*
@@ -148,9 +148,9 @@ void raminit(struct romstage_params *params)
 
 	/* Display SMM area */
 	if (CONFIG(HAVE_SMI_HANDLER)) {
-		smm_region((void **)&smm_base, &smm_size);
+		smm_region(&smm_base, &smm_size);
 		printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
-		printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
+		printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base);
 	}
 
 	/* Migrate CAR data */
@@ -238,7 +238,7 @@ void raminit(struct romstage_params *params)
 		printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n");
 
 		if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) {
-			size_t delta_bytes = (unsigned int)smm_base
+			size_t delta_bytes = smm_base
 				- cbmem_root->PhysicalStart
 				- cbmem_root->ResourceLength;
 			printk(BIOS_ERR,

src/drivers/intel/fsp1_1/ramstage.c

@@ -33,19 +33,19 @@ __weak void soc_after_silicon_init(void)
 /* Display SMM memory map */
 static void smm_memory_map(void)
 {
-	void *base;
+	uintptr_t base;
 	size_t size;
 	int i;
 
 	printk(BIOS_SPEW, "SMM Memory Map\n");
 
 	smm_region(&base, &size);
-	printk(BIOS_SPEW, "SMRAM       : %p 0x%zx\n", base, size);
+	printk(BIOS_SPEW, "SMRAM       : 0x%zx 0x%zx\n", base, size);
 
 	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
 		if (smm_subregion(i, &base, &size))
 			continue;
-		printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size);
+		printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
 	}
 }
 

src/include/cpu/x86/smm.h

@@ -587,7 +587,7 @@ void restore_default_smm_area(void *smm_save_area);
  * Fills in the arguments for the entire SMM region covered by chipset
  * protections. e.g. TSEG.
  */
-void smm_region(void **start, size_t *size);
+void smm_region(uintptr_t *start, size_t *size);
 
 enum {
 	/* SMM handler area. */
@@ -602,6 +602,6 @@ enum {
 
 /* Fills in the start and size for the requested SMM subregion. Returns
  * 0 on success, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);
 
 #endif /* CPU_X86_SMM_H */

src/soc/amd/picasso/cpu.c

@@ -63,21 +63,21 @@ static int get_cpu_count(void)
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
 	size_t handler_size;
 
 	/* Initialize global tracking state. */
 	smm_region(&smm_base, &smm_size);
 	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
 
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
 	relo_attrs.tseg_base = relo_attrs.smbase;
 	relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
 	relo_attrs.tseg_mask |= SMM_TSEG_WB;
 
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
 	*perm_smsize = handler_size;
 	*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }

src/soc/amd/picasso/ramtop.c

@@ -81,9 +81,9 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
 	*size = smm_region_size();
 }
 
@@ -109,15 +109,13 @@ static void clear_tvalid(void)
 	wrmsr(SMM_MASK_MSR, mask);
 }
 
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
 	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
 
 	switch (sub) {

src/soc/amd/picasso/romstage.c

@@ -43,9 +43,8 @@ asmlinkage void car_stage_entry(void)
 {
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
-	uintptr_t tseg_base;
 	int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
 
 	console_init();
@@ -92,8 +91,7 @@ asmlinkage void car_stage_entry(void)
 	 * region for other purposes.
 	 */
 	smm_region(&smm_base, &smm_size);
-	tseg_base = (uintptr_t)smm_base;
-	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
 
 	post_code(0x45);
 	run_postcar_phase(&pcf);

src/soc/amd/stoneyridge/cpu.c

@@ -63,21 +63,21 @@ static int get_cpu_count(void)
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
 	size_t handler_size;
 
 	/* Initialize global tracking state. */
 	smm_region(&smm_base, &smm_size);
 	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
 
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
 	relo_attrs.tseg_base = relo_attrs.smbase;
 	relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
 	relo_attrs.tseg_mask |= SMM_TSEG_WB;
 
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
 	*perm_smsize = handler_size;
 	*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }

src/soc/amd/stoneyridge/ramtop.c

@@ -81,9 +81,9 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
 	*size = smm_region_size();
 }
 
@@ -109,15 +109,13 @@ static void clear_tvalid(void)
 	wrmsr(SMM_MASK_MSR, mask);
 }
 
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
 	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
 
 	switch (sub) {
@@ -135,8 +133,7 @@ int smm_subregion(int sub, void **start, size_t *size)
 		return -1;
 	}
 
-	*start = (void *)sub_base;
+	*start = sub_base;
 	*size = sub_size;
-
 	return 0;
 }

src/soc/amd/stoneyridge/romstage.c

@@ -84,9 +84,8 @@ asmlinkage void car_stage_entry(void)
 {
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
-	uintptr_t tseg_base;
 	msr_t base, mask;
 	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
 	int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@@ -177,8 +176,7 @@ asmlinkage void car_stage_entry(void)
 	 * region for other purposes.
 	 */
 	smm_region(&smm_base, &smm_size);
-	tseg_base = (uintptr_t)smm_base;
-	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
 
 	post_code(0x45);
 	run_postcar_phase(&pcf);

src/soc/intel/apollolake/cpu.c

@@ -205,9 +205,9 @@ void get_microcode_info(const void **microcode, int *parallel)
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
 	size_t handler_size;
 
 	/* All range registers are aligned to 4KiB */
@@ -217,12 +217,12 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	smm_region(&smm_base, &smm_size);
 	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
 
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
 	relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
 	relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
 	relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
 
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
 	*perm_smsize = handler_size;
 	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }

src/soc/intel/apollolake/memmap.c

@@ -43,23 +43,19 @@ void *cbmem_top(void)
 	return tolum;
 }
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
 	*size = sa_get_tseg_size();
 }
 
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
-	void *smm_base;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
-
-	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+	smm_region(&sub_base, &sub_size);
 
 	switch (sub) {
 	case SMM_SUBREGION_HANDLER:
@@ -75,8 +71,7 @@ int smm_subregion(int sub, void **start, size_t *size)
 		return -1;
 	}
 
-	*start = (void *)sub_base;
+	*start = sub_base;
 	*size = sub_size;
-
 	return 0;
 }

src/soc/intel/apollolake/romstage.c

@@ -202,10 +202,9 @@ asmlinkage void car_stage_entry(void)
 	uintptr_t top_of_ram;
 	bool s3wake;
 	struct chipset_power_state *ps = pmc_get_power_state();
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size, var_size;
 	const void *new_var_data;
-	uintptr_t tseg_base;
 
 	timestamp_add_now(TS_START_ROMSTAGE);
 
@@ -258,8 +257,7 @@ asmlinkage void car_stage_entry(void)
 	* region for other purposes.
 	*/
 	smm_region(&smm_base, &smm_size);
-	tseg_base = (uintptr_t)smm_base;
-	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
 
 	run_postcar_phase(&pcf);
 }

src/soc/intel/braswell/cpu.c

@@ -150,7 +150,7 @@ static int get_cpu_count(void)
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
 
 	/* All range registers are aligned to 4KiB */
@@ -158,7 +158,7 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 
 	/* Initialize global tracking state. */
 	smm_region(&smm_base, &smm_size);
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
 	relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
 	relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
 	relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;

src/soc/intel/braswell/memmap.c

@@ -28,9 +28,9 @@ static size_t smm_region_size(void)
 	return smm_size;
 }
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20);
+	*start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
 	*size = smm_region_size();
 }
 
@@ -43,15 +43,13 @@ void smm_region(void **start, size_t *size)
  *     |         (TSEG)          |
  *     +-------------------------+ BUNIT_SMRRL
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
-	void *sub_ptr;
 	size_t sub_size;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	smm_region(&sub_ptr, &sub_size);
-	sub_base = (uintptr_t)sub_ptr;
+	smm_region(&sub_base, &sub_size);
 
 	switch (sub) {
 	case SMM_SUBREGION_HANDLER:
@@ -67,15 +65,14 @@ int smm_subregion(int sub, void **start, size_t *size)
 		return -1;
 	}
 
-	*start = (void *)sub_base;
+	*start = sub_base;
 	*size = sub_size;
-
 	return 0;
 }
 
 void *cbmem_top(void)
 {
-	char *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
 
 	/*
@@ -106,6 +103,6 @@ void *cbmem_top(void)
 	 *     +-------------------------+
 	*/
 
-	smm_region((void **)&smm_base, &smm_size);
+	smm_region(&smm_base, &smm_size);
 	return (void *)smm_base;
 }

src/soc/intel/braswell/northcluster.c

@@ -87,7 +87,7 @@ static void nc_read_resources(struct device *dev)
 	unsigned long mmconf;
 	unsigned long bmbound_k;
 	unsigned long bmbound_hi;
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
 	unsigned long tseg_base_k;
 	unsigned long tseg_top_k;
@@ -102,7 +102,7 @@ static void nc_read_resources(struct device *dev)
 
 	/* Determine TSEG data */
 	smm_region(&smm_base, &smm_size);
-	tseg_base_k = RES_IN_KIB((unsigned long) smm_base);
+	tseg_base_k = RES_IN_KIB(smm_base);
 	tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size);
 
 	/* Determine the base of the FSP reserved memory */

src/soc/intel/cannonlake/include/soc/smm.h

@@ -29,10 +29,10 @@ struct ied_header {
 } __packed;
 
 struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t smram_base;
+	size_t smram_size;
+	uintptr_t ied_base;
+	size_t ied_size;
 	msr_t smrr_base;
 	msr_t smrr_mask;
 	msr_t emrr_base;

src/soc/intel/cannonlake/memmap.c

@@ -29,9 +29,9 @@
 
 #include "chip.h"
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
 	*size = sa_get_tseg_size();
 }
 
@@ -46,16 +46,14 @@ void smm_region(void **start, size_t *size)
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
-	void *smm_base;
 	const size_t ied_size = CONFIG_IED_REGION_SIZE;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);
 
 	switch (sub) {
 	case SMM_SUBREGION_HANDLER:
@@ -77,9 +75,8 @@ int smm_subregion(int sub, void **start, size_t *size)
 		return -1;
 	}
 
-	*start = (void *)sub_base;
+	*start = sub_base;
 	*size = sub_size;
-
 	return 0;
 }
 

src/soc/intel/cannonlake/smmrelocate.c

@@ -173,11 +173,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
-	void *tseg_base;
+	uintptr_t tseg_base;
 	size_t tseg_size;
 	u32 emrr_base;
 	u32 emrr_size;
@@ -192,14 +188,8 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	phys_bits = cpu_phys_address_size();
 
 	smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
 
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */
 	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
@@ -242,8 +232,8 @@ static void setup_ied_area(struct smm_relocation_params *params)
 
 	ied_base = (void *)params->ied_base;
 
-	printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
-	printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);
 
 	/* Place IED header at IEDBASE. */
 	memcpy(ied_base, &ied, sizeof(ied));

src/soc/intel/denverton_ns/cpu.c

@@ -126,9 +126,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 			 size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
 	size_t handler_size;
 
 	/* All range registers are aligned to 4KiB */
@@ -138,12 +138,12 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 	smm_region(&smm_base, &smm_size);
 	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
 
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
 	relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
 	relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
 	relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
 
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
 	*perm_smsize = handler_size;
 	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }

src/soc/intel/denverton_ns/memmap.c

@@ -70,21 +70,19 @@ static inline size_t smm_region_size(void)
 	return system_agent_region_base(TOLUD) - smm_region_start();
 }
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
 	*size = smm_region_size();
 }
 
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
 	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
 
 	switch (sub) {
@@ -101,8 +99,7 @@ int smm_subregion(int sub, void **start, size_t *size)
 		return -1;
 	}
 
-	*start = (void *)sub_base;
+	*start = sub_base;
 	*size = sub_size;
-
 	return 0;
 }

src/soc/intel/denverton_ns/romstage.c

@@ -141,9 +141,8 @@ asmlinkage void car_stage_entry(void)
 
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
-	void *smm_base;
+	uintptr_t smm_base;
 	size_t smm_size;
-	uintptr_t tseg_base;
 
 	console_init();
 
@@ -183,8 +182,7 @@ asmlinkage void car_stage_entry(void)
 	 */
 	if (CONFIG(HAVE_SMI_HANDLER)) {
 		smm_region(&smm_base, &smm_size);
-		tseg_base = (uintptr_t)smm_base;
-		postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+		postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
 	}
 
 	run_postcar_phase(&pcf);

src/soc/intel/icelake/include/soc/smm.h

@@ -28,10 +28,10 @@ struct ied_header {
 } __packed;
 
 struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t smram_base;
+	size_t smram_size;
+	uintptr_t ied_base;
+	size_t ied_size;
 	msr_t smrr_base;
 	msr_t smrr_mask;
 	msr_t emrr_base;

src/soc/intel/icelake/memmap.c

@@ -27,9 +27,9 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
 	*size = sa_get_tseg_size();
 }
 
@@ -44,16 +44,14 @@ void smm_region(void **start, size_t *size)
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
-	void *smm_base;
 	const size_t ied_size = CONFIG_IED_REGION_SIZE;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);
 
 	switch (sub) {
 	case SMM_SUBREGION_HANDLER:
@@ -75,9 +73,8 @@ int smm_subregion(int sub, void **start, size_t *size)
 		return -1;
 	}
 
-	*start = (void *)sub_base;
+	*start = sub_base;
 	*size = sub_size;
-
 	return 0;
 }
 

src/soc/intel/icelake/smmrelocate.c

@@ -172,11 +172,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
-	void *tseg_base;
+	uintptr_t tseg_base;
 	size_t tseg_size;
 	u32 emrr_base;
 	u32 emrr_size;
@@ -191,14 +187,8 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	phys_bits = cpu_phys_address_size();
 
 	smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
 
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */
 	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
@@ -241,8 +231,8 @@ static void setup_ied_area(struct smm_relocation_params *params)
 
 	ied_base = (void *)params->ied_base;
 
-	printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
-	printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);
 
 	/* Place IED header at IEDBASE. */
 	memcpy(ied_base, &ied, sizeof(ied));

src/soc/intel/skylake/include/soc/smm.h

@@ -30,10 +30,10 @@ struct ied_header {
 } __packed;
 
 struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t smram_base;
+	size_t smram_size;
+	uintptr_t ied_base;
+	size_t ied_size;
 	msr_t smrr_base;
 	msr_t smrr_mask;
 	msr_t emrr_base;

src/soc/intel/skylake/memmap.c

@@ -25,14 +25,15 @@
 #include <intelblocks/systemagent.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/smm.h>
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
 #include "chip.h"
 
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
 	*size = sa_get_tseg_size();
 }
 
@@ -47,16 +48,14 @@ void smm_region(void **start, size_t *size)
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
 	uintptr_t sub_base;
 	size_t sub_size;
-	void *smm_base;
 	const size_t ied_size = CONFIG_IED_REGION_SIZE;
 	const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
 
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);
 
 	switch (sub) {
 	case SMM_SUBREGION_HANDLER:
@@ -78,9 +77,8 @@ int smm_subregion(int sub, void **start, size_t *size)
 		return -1;
 	}
 
-	*start = (void *)sub_base;
+	*start = sub_base;
 	*size = sub_size;
-
 	return 0;
 }
 

src/soc/intel/skylake/romstage/romstage_fsp20.c

@@ -173,9 +173,8 @@ asmlinkage void car_stage_entry(void)
 	postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
 
 	if (CONFIG(HAVE_SMI_HANDLER)) {
-		void *smm_base;
+		uintptr_t smm_base;
 		size_t smm_size;
-		uintptr_t tseg_base;
 
 		/*
 		 * Cache the TSEG region at the top of ram. This region is
@@ -185,8 +184,7 @@ asmlinkage void car_stage_entry(void)
 		 * region for other purposes.
 		 */
 		smm_region(&smm_base, &smm_size);
-		tseg_base = (uintptr_t)smm_base;
-		postcar_frame_add_mtrr(&pcf, tseg_base, smm_size,
+		postcar_frame_add_mtrr(&pcf, smm_base, smm_size,
 					MTRR_TYPE_WRBACK);
 	}
 

src/soc/intel/skylake/smmrelocate.c

@@ -182,11 +182,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
-	void *tseg_base;
+	uintptr_t tseg_base;
 	size_t tseg_size;
 	u32 emrr_base;
 	u32 emrr_size;
@@ -201,14 +197,8 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	phys_bits = cpuid_eax(0x80000008) & 0xff;
 
 	smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
 
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */
 	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
@@ -251,8 +241,8 @@ static void setup_ied_area(struct smm_relocation_params *params)
 
 	ied_base = (void *)params->ied_base;
 
-	printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
-	printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32) params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32) params->ied_size);
 
 	/* Place IED header at IEDBASE. */
 	memcpy(ied_base, &ied, sizeof(ied));