soc/intel/cannonlake: enable pch link in bootblock
This moves the call to pch_enable_lpc() from romstage to bootblock. In other words, it happens earlier in the boot process. Turns out, we need this to talk to the EC to determine if we're in recovery mode or not. BUG=b:69011806 TEST=boots to linux Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -18,6 +18,7 @@ bootblock-y += gspi.c
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bootblock-y += i2c.c
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bootblock-y += memmap.c
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bootblock-y += spi.c
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bootblock-y += lpc.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
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@ -17,6 +17,7 @@
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#include <device/device.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/pmclib.h>
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@ -174,6 +175,9 @@ void pch_early_iorange_init(void)
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dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;
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pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
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pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
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/* Program generic IO Decode Range */
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pch_enable_lpc();
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}
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void pch_early_init(void)
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@ -22,7 +22,6 @@
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#include <console/console.h>
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#include <fsp/util.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pmclib.h>
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#include <memory_info.h>
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#include <soc/iomap.h>
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@ -47,8 +46,6 @@ asmlinkage void car_stage_entry(void)
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/* initialize Heci interface */
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heci_init(HECI1_BASE_ADDRESS);
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/* Program LPC generic decoding */
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pch_enable_lpc();
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timestamp_add_now(TS_START_ROMSTAGE);
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s3wake = pmc_fill_power_state(ps) == ACPI_S3;
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fsp_memory_init(s3wake);
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