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soc/intel/cannonlake: enable pch link in bootblock 

This moves the call to pch_enable_lpc() from romstage to bootblock.
In other words, it happens earlier in the boot process.  Turns out, we
need this to talk to the EC to determine if we're in recovery mode or
not.

BUG=b:69011806
TEST=boots to linux

Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Caveh Jalali 2018-01-23 22:15:24 -08:00 committed by Aaron Durbin
parent 6de0cd2b7d
commit 1428f0176d
3 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/cannonlake/Makefile.inc
View File

@ -18,6 +18,7 @@ bootblock-y += gspi.c
bootblock-y += i2c.c bootblock-y += i2c.c
bootblock-y += memmap.c bootblock-y += memmap.c
bootblock-y += spi.c bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c

4
src/soc/intel/cannonlake/bootblock/pch.c
View File

@ -17,6 +17,7 @@
#include <device/device.h> #include <device/device.h>
#include <intelblocks/fast_spi.h> #include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h> #include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <intelblocks/rtc.h> #include <intelblocks/rtc.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
@ -174,6 +175,9 @@ void pch_early_iorange_init(void)
dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN; dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en); pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en); pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
/* Program generic IO Decode Range */
pch_enable_lpc();
} }
void pch_early_init(void) void pch_early_init(void)

3
src/soc/intel/cannonlake/romstage/romstage.c
View File

@ -22,7 +22,6 @@
#include <console/console.h> #include <console/console.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <memory_info.h> #include <memory_info.h>
#include <soc/iomap.h> #include <soc/iomap.h>
@ -47,8 +46,6 @@ asmlinkage void car_stage_entry(void)
/* initialize Heci interface */ /* initialize Heci interface */
heci_init(HECI1_BASE_ADDRESS); heci_init(HECI1_BASE_ADDRESS);
/* Program LPC generic decoding */
pch_enable_lpc();
timestamp_add_now(TS_START_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake); fsp_memory_init(s3wake);