cpu/x86: Fix MSR_PLATFORM_INFO definition

While common to many Intel CPUs, this is not an architectural
MSR that should be globally defined for all x86.

Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian

src/include/cpu/x86/tsc.h

@@ -11,8 +11,6 @@
 #define TSC_SYNC
 #endif
 
-#define MSR_PLATFORM_INFO 0xce
-
 struct tsc_struct {
 	unsigned int lo;
 	unsigned int hi;

src/northbridge/intel/fsp_rangeley/udelay.c

@@ -18,6 +18,8 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 
+#define MSR_PLATFORM_INFO 0xce
+
 /**
  * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
  */