AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes

Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4524
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/cpu/amd/car/post_cache_as_ram.c

@@ -77,7 +77,7 @@ static void vErrata343(void)
 
 void cache_as_ram_switch_stack(void *resume_backup_memory);
 
-static void post_cache_as_ram(void)
+void post_cache_as_ram(void)
 {
 	void *resume_backup_memory = NULL;
 #if 1

src/cpu/amd/model_10xxx/init_cpus.c

@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include "cpu/amd/car/post_cache_as_ram.c"
 #include "defaults.h"
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>

src/cpu/amd/model_fxx/init_cpus.c

@@ -1,3 +1,5 @@
+#include "cpu/amd/car/post_cache_as_ram.c"
+
 #if CONFIG_HAVE_OPTION_TABLE
 #include "option_table.h"
 #endif

src/include/lib.h

@@ -54,6 +54,7 @@ void cache_as_ram_main(void);
 #else
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 #endif
+void post_cache_as_ram(void);
 
 /* Defined in src/lib/hexdump.c */
 void hexdump(unsigned long memory, int length);

src/mainboard/advansus/a785e-i/romstage.c

@@ -63,7 +63,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"

src/mainboard/amd/bimini_fam10/romstage.c

@@ -62,7 +62,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/amd/dbm690t/romstage.c

@@ -58,7 +58,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/amd/mahogany/romstage.c

@@ -59,7 +59,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -62,7 +62,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/amd/pistachio/romstage.c

@@ -53,7 +53,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -77,7 +77,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -83,7 +83,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -61,7 +61,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/arima/hdama/romstage.c

@@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/asrock/939a785gmh/romstage.c

@@ -63,7 +63,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/asus/a8n_e/romstage.c

@@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "southbridge/nvidia/ck804/early_setup_ss.h"
 #include "southbridge/nvidia/ck804/early_setup.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -83,7 +83,6 @@ void soft_reset(void)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"

src/mainboard/asus/a8v-e_se/romstage.c

@@ -83,7 +83,6 @@ void soft_reset(void)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"

src/mainboard/asus/k8v-x/romstage.c

@@ -81,7 +81,6 @@ void soft_reset(void)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"

src/mainboard/asus/m2n-e/romstage.c

@@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/dualcore/dualcore.c"
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #define SB_VFSMAF 0

src/mainboard/asus/m2v/romstage.c

@@ -68,7 +68,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"

src/mainboard/asus/m4a78-em/romstage.c

@@ -61,7 +61,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/asus/m4a785-m/romstage.c

@@ -61,7 +61,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/asus/m5a88-v/romstage.c

@@ -63,7 +63,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"

src/mainboard/avalue/eax-785e/romstage.c

@@ -63,7 +63,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"

src/mainboard/broadcom/blast/romstage.c

@@ -54,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
 #include "southbridge/sis/sis966/early_setup_ss.h"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/gigabyte/m57sli/romstage.c

@@ -74,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -57,7 +57,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -57,7 +57,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -61,7 +61,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/hp/dl145_g1/romstage.c

@@ -81,7 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #define RC0 ((1<<1)<<8)

src/mainboard/hp/dl145_g3/romstage.c

@@ -78,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include <spd.h>
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -77,7 +77,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/pci.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/ibm/e325/romstage.c

@@ -56,7 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/ibm/e326/romstage.c

@@ -56,7 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -63,7 +63,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/iwill/dk8_htx/romstage.c

@@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 

src/mainboard/iwill/dk8s2/romstage.c

@@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 

src/mainboard/iwill/dk8x/romstage.c

@@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 

src/mainboard/jetway/pa78vm5/romstage.c

@@ -68,7 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/kontron/kt690/romstage.c

@@ -60,7 +60,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/msi/ms7135/romstage.c

@@ -63,7 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "southbridge/nvidia/ck804/early_setup_ss.h"
 #include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/msi/ms7260/romstage.c

@@ -76,7 +76,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/msi/ms9185/romstage.c

@@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/msi/ms9282/romstage.c

@@ -89,7 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 // Disabled until it's actually used:
 // #include "cpu/amd/model_fxx/fidvid.c"

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -70,7 +70,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/newisys/khepri/romstage.c

@@ -62,7 +62,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/siemens/sitemp_g1p1/romstage.c

@@ -76,7 +76,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/sunw/ultra40/romstage.c

@@ -63,7 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
 #include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/supermicro/h8dme/romstage.c

@@ -126,7 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/dualcore/dualcore.c"
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/supermicro/h8dmr/romstage.c

@@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/dualcore/dualcore.c"
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -63,7 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/quadcore/quadcore.c"
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/quadcore/quadcore.c"
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -63,7 +63,6 @@ static int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdfam10/pci.c"
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "northbridge/amd/amdfam10/early_ht.c"

src/mainboard/technexion/tim5690/romstage.c

@@ -58,7 +58,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "tn_post_code.c"

src/mainboard/technexion/tim8690/romstage.c

@@ -58,7 +58,6 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/tyan/s2850/romstage.c

@@ -52,7 +52,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/tyan/s2875/romstage.c

@@ -52,7 +52,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/tyan/s2880/romstage.c

@@ -52,7 +52,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/tyan/s2881/romstage.c

@@ -51,7 +51,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/tyan/s2882/romstage.c

@@ -52,7 +52,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/tyan/s2885/romstage.c

@@ -51,7 +51,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/tyan/s2891/romstage.c

@@ -38,7 +38,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/dualcore/dualcore.c"
 #include "southbridge/nvidia/ck804/early_setup_ss.h"
 #include "southbridge/nvidia/ck804/early_setup.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2892/romstage.c

@@ -45,7 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
 #include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2895/romstage.c

@@ -63,7 +63,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
 #include "southbridge/nvidia/ck804/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2912/romstage.c

@@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/early_ht.c"

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -71,7 +71,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode.h"
 
 #include "cpu/amd/model_10xxx/init_cpus.c"

src/mainboard/tyan/s4880/romstage.c

@@ -71,7 +71,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #define RC0 ((1<<2)<<8)

src/mainboard/tyan/s4882/romstage.c

@@ -79,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #define RC0 ((1<<2)<<8)

src/mainboard/winent/mb6047/romstage.c

@@ -37,7 +37,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/dualcore/dualcore.c"
 #include "southbridge/nvidia/ck804/early_setup_ss.h"
 #include "southbridge/nvidia/ck804/early_setup.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #if CONFIG_SET_FIDVID
 #include "cpu/amd/model_fxx/fidvid.c"