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mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support for burnet/esche 

Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB

BUG=b:165956924
BRANCH=kukui
TEST=emerge-jacuzzi coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kevin Chiu 2020-08-26 18:10:33 +08:00 committed by Hung-Te Lin
parent 9256e51f48
commit 144c5aeca2
3 changed files with 29 additions and 0 deletions
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1
src/mainboard/google/kukui/sdram_configs.c
View File

@ -24,6 +24,7 @@ static const char *const sdram_configs[] = {
[0x0a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", [0x0a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB",
/* Table shared by Burnet and its variants, offset = 0x10 */ /* Table shared by Burnet and its variants, offset = 0x10 */
[0x10] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB",
[0x11] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", [0x11] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB",
[0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", [0x12] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB",
[0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", [0x13] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB",

1
src/mainboard/google/kukui/sdram_params/Makefile.inc
View File

@ -1,4 +1,5 @@
sdram-params := sdram-params :=
sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB
sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB
sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB
sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB

27
src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/dramc_param.h>
struct sdram_params params = {
.source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
.frequency = 1600,
.ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2,
.wr_level = {
[CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} },
[CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} }
},
.cbt_cs_dly = {
[CHANNEL_A] = {0x6, 0x5},
[CHANNEL_B] = {0x6, 0x6}
},
.cbt_final_vref = {
[CHANNEL_A] = {0x56, 0x58},
[CHANNEL_B] = {0x58, 0x56}
},
.emi_cona_val = 0xF053F154,
.emi_conh_val = 0x44440003,
.emi_conf_val = 0x00421000,
.chn_emi_cona_val = {0x0444F051, 0x0444F051},
.cbt_mode_extern = CBT_NORMAL_MODE,
.delay_cell_unit = 868,
};