Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Vladimir Serbinenko
Martin Roth
parent
c37c7c8b1f
commit
144eea0697
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@ -253,8 +253,8 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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config FLASHMAP_OFFSET
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hex "Flash Map Offset"
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default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
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default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
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default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
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default CBFS_SIZE if !ARCH_X86
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default 0
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help
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@ -20,9 +20,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
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subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B
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subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += model_206ax
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += model_206ax
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax
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@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select INTEL_INT15
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SYSTEM_TYPE_LAPTOP
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA1155
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_ITE_IT8728F
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select BOARD_ROMSIZE_KB_8192
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA1155
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_ITE_IT8728F
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select BOARD_ROMSIZE_KB_8192
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select EC_QUANTA_ENE_KB3940Q
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select BOARD_ROMSIZE_KB_8192
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@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SOUTHBRIDGE_INTEL_C216
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select BOARD_ROMSIZE_KB_8192
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select EC_GOOGLE_CHROMEEC
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@ -16,6 +16,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SERIRQ_CONTINUOUS_MODE
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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config USE_NATIVE_RAMINIT
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bool
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default n
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config CHROMEOS
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select CHROMEOS_VBNV_CMOS
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select LID_SWITCH
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@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SOUTHBRIDGE_INTEL_C216
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select EC_COMPAL_ENE932
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select BOARD_ROMSIZE_KB_8192
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@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge
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register "gpu_cpu_backlight" = "0x000001d4"
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register "gpu_pch_backlight" = "0x03aa0000"
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register "max_mem_clock_mhz" = "666"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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@ -28,6 +28,7 @@
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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@ -158,6 +159,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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*pei_data = pei_data_template;
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* enabled power usb oc pin */
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{ 0, 0, -1 }, /* P0: Empty */
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{ 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
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{ 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
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{ 1, 0, 1 }, /* P3: Left USB 3 (OC1) */
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{ 0, 0, -1 }, /* P4: Empty */
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{ 0, 0, -1 }, /* P5: Empty */
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{ 0, 0, -1 }, /* P6: Empty */
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{ 0, 0, -1 }, /* P7: Empty */
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/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
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{ 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */
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{ 0, 0, -1 }, /* P9: Empty */
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{ 1, 0, -1 }, /* P10: Camera (no OC) */
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{ 0, 0, -1 }, /* P11: Empty */
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{ 0, 0, -1 }, /* P12: Empty */
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{ 0, 0, -1 }, /* P13: Empty */
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};
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void mainboard_get_spd(spd_raw_data *spd) {
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read_spd(&spd[0], 0x50);
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read_spd(&spd[2], 0x52);
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}
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void mainboard_config_superio(void)
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{
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}
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@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SOUTHBRIDGE_INTEL_C216
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select EC_QUANTA_IT8518
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select BOARD_ROMSIZE_KB_8192
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@ -17,6 +17,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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select IVYBRIDGE_LVDS
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config USE_NATIVE_RAMINIT
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bool
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default n
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config CHROMEOS
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select CHROMEOS_VBNV_CMOS
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@ -3,7 +3,7 @@ if BOARD_INTEL_EMERALDLAKE2
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_SMSC_SIO1007
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select BOARD_ROMSIZE_KB_8192
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@ -13,6 +13,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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#select MAINBOARD_HAS_CHROMEOS
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config USE_NATIVE_RAMINIT
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bool
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default n
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config CHROMEOS
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#select CHROMEOS_VBNV_CMOS
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@ -3,7 +3,7 @@ if BOARD_KONTRON_KTQM77
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_WINBOND_W83627DHG
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select EC_KONTRON_IT8516E
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@ -14,6 +14,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select ENABLE_VMX
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select HAVE_MRC
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config USE_NATIVE_RAMINIT
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bool
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default n
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config MAINBOARD_DIR
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string
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default kontron/ktqm77
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA988B
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_BD82X6X
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA988B
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_BD82X6X
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_C216
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_SMSC_MEC1308
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# LPC47N207 selected for external LPC card
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@ -21,6 +21,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select INTEL_INT15
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select HAVE_MRC
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config USE_NATIVE_RAMINIT
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bool
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default n
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config CHROMEOS
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select CHROMEOS_VBNV_CMOS
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@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_ITE_IT8772F
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# LPC47N207 selected for external LPC card
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@ -18,6 +18,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_MRC
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select INTEL_INT15
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config USE_NATIVE_RAMINIT
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bool
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default n
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config CHROMEOS
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select PHYSICAL_REC_SWITCH
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select CHROMEOS_VBNV_CMOS
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@ -13,12 +13,6 @@
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## GNU General Public License for more details.
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##
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config NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
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bool
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select CPU_INTEL_MODEL_206AX
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select INTEL_GMA_ACPI
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config NORTHBRIDGE_INTEL_SANDYBRIDGE
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bool
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@ -28,13 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
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select HAVE_DEBUG_RAM_SETUP
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select INTEL_GMA_ACPI
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config NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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bool
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select CPU_INTEL_MODEL_306AX
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select INTEL_GMA_ACPI
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config NORTHBRIDGE_INTEL_IVYBRIDGE
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bool
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select MMCONF_SUPPORT
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@ -43,7 +30,14 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
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select HAVE_DEBUG_RAM_SETUP
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select INTEL_GMA_ACPI
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if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
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if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
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config USE_NATIVE_RAMINIT
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bool "Use native raminit"
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default y
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help
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Select if you want to use coreboot implementation of raminit rather than
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System Agent/MRC.bin. You should answer Y.
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config CBFS_SIZE
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hex
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@ -79,10 +73,8 @@ config MRC_CACHE_SIZE
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config DCACHE_RAM_BASE
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hex
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default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
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default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
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default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE
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default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
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default 0xff7e0000 if !USE_NATIVE_RAMINIT
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default 0xfefe0000 if USE_NATIVE_RAMINIT
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config DCACHE_RAM_SIZE
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hex
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@ -98,7 +90,7 @@ config DCACHE_RAM_MRC_VAR_SIZE
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config HAVE_MRC
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bool "Add a System Agent binary"
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depends on !NORTHBRIDGE_INTEL_IVYBRIDGE && !NORTHBRIDGE_INTEL_SANDYBRIDGE
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depends on !USE_NATIVE_RAMINIT
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help
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Select this option to add a System Agent binary to
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the resulting coreboot image.
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@ -13,7 +13,7 @@
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# GNU General Public License for more details.
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#
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC),y)
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y)
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ramstage-y += ram_calc.c
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ramstage-y += northbridge.c
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@ -25,12 +25,12 @@ ramstage-y += acpi.c
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ramstage-y += mrccache.c
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romstage-y += ram_calc.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += raminit_mrc.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += raminit_mrc.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ../../../device/dram/ddr3.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ../../../device/dram/ddr3.c
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ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
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romstage-y += raminit.c
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romstage-y += ../../../device/dram/ddr3.c
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else
|
||||
romstage-y += raminit_mrc.c
|
||||
endif
|
||||
romstage-y += romstage.c
|
||||
romstage-y += mrccache.c
|
||||
romstage-y += iommu.c
|
||||
|
|
|
|||
|
|
@ -70,8 +70,7 @@ void main(unsigned long bist)
|
|||
mainboard_config_superio();
|
||||
|
||||
/* USB is inited in MRC if MRC is used. */
|
||||
if (!(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
|
||||
|| CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC)) {
|
||||
if (CONFIG_USE_NATIVE_RAMINIT) {
|
||||
early_usb_init(mainboard_usb_ports);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -46,10 +46,11 @@ romstage-y += reset.c
|
|||
romstage-y += early_spi.c early_pch_common.c
|
||||
romstage-y += early_rcba.c
|
||||
|
||||
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c
|
||||
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c
|
||||
romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c
|
||||
romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c
|
||||
ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
|
||||
romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c
|
||||
else
|
||||
romstage-y += early_me_mrc.c early_usb_mrc.c
|
||||
endif
|
||||
|
||||
ramstage-y += madt.c
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev)
|
|||
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
|
||||
|
||||
/* For others, done in MRC. */
|
||||
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
|
||||
#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
|
||||
pci_write_config32(dev, 0x84, 0x930c8811);
|
||||
pci_write_config32(dev, 0x88, 0x24000d30);
|
||||
pci_write_config32(dev, 0xf4, 0x80408588);
|
||||
|
|
@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev)
|
|||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
|
||||
/* For others, done in MRC. */
|
||||
#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)
|
||||
#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
|
||||
struct resource *res;
|
||||
u8 access_cntl;
|
||||
|
||||
|
|
|
|||
|
|
@ -114,6 +114,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
|
|||
|
||||
KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true
|
||||
KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true
|
||||
KconfigBool["USE_NATIVE_RAMINIT"] = true
|
||||
KconfigBool["INTEL_INT15"] = true
|
||||
KconfigBool["HAVE_ACPI_TABLES"] = true
|
||||
KconfigBool["HAVE_ACPI_RESUME"] = true
|
||||
|
|
|
|||
|
|
@ -326,9 +326,9 @@ EOF
|
|||
case $northbridge in
|
||||
INTEL_HASWELL)
|
||||
cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7";;
|
||||
INTEL_IVYBRIDGE|INTEL_IVYBRIDGE_MRC|INTEL_FSP_IVYBRIDGE)
|
||||
INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE)
|
||||
cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7";;
|
||||
INTEL_SANDYBRIDGE|INTEL_SANDYBRIDGE_MRC)
|
||||
INTEL_SANDYBRIDGE)
|
||||
cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7";;
|
||||
*)
|
||||
cpu_nice="$northbridge";;
|
||||
|
|
|
|||
Loading…
Reference in New Issue