soc/intel/common/block/gpio: add code for NMI enabling
Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -79,6 +79,9 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current)
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current +=
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acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
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/* NMI */
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
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return current;
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}
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@ -48,6 +48,10 @@
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((group) * sizeof(uint32_t)))
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#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \
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((group) * sizeof(uint32_t)))
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#define GPI_NMI_STS_OFFSET(comm, group) ((comm)->gpi_nmi_sts_reg_0 + \
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((group) * sizeof(uint32_t)))
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#define GPI_NMI_EN_OFFSET(comm, group) ((comm)->gpi_nmi_en_reg_0 + \
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((group) * sizeof(uint32_t)))
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#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \
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((group) * sizeof(uint32_t)))
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#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \
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@ -176,6 +180,35 @@ static void gpi_enable_smi(const struct pad_config *cfg,
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pcr_or32(comm->port, en_reg, en_value);
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}
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static void gpi_enable_nmi(const struct pad_config *cfg,
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const struct pad_community *comm)
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{
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uint16_t sts_reg;
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uint16_t en_reg;
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uint32_t en_value;
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int group;
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int pin;
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if (((cfg->pad_config[0]) & PAD_CFG0_ROUTE_NMI) != PAD_CFG0_ROUTE_NMI)
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return;
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/* Do not configure NMI if the platform doesn't support it */
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if (!comm->gpi_nmi_sts_reg_0 || !comm->gpi_nmi_en_reg_0)
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return;
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pin = relative_pad_in_comm(comm, cfg->pad);
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group = gpio_group_index(comm, pin);
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sts_reg = GPI_NMI_STS_OFFSET(comm, group);
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en_reg = GPI_NMI_EN_OFFSET(comm, group);
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en_value = gpio_bitmask_within_group(comm, pin);
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/* Write back 1 to reset the sts bit */
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pcr_rmw32(comm->port, sts_reg, en_value, 0);
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/* Set enable bits */
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pcr_or32(comm->port, en_reg, en_value);
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}
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static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port,
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uint16_t pad_cfg_offset)
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{
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@ -283,6 +316,7 @@ static void gpio_configure_pad(const struct pad_config *cfg)
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gpio_configure_itss(cfg, comm->port, config_offset);
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gpio_configure_owner(cfg, comm);
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gpi_enable_smi(cfg, comm);
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gpi_enable_nmi(cfg, comm);
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}
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void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
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@ -111,6 +111,8 @@ struct pad_community {
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uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */
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uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */
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uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */
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uint16_t gpi_nmi_sts_reg_0; /* offset to GPI NMI STS Reg 0 */
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uint16_t gpi_nmi_en_reg_0; /* offset to GPI NMI EN Reg 0 */
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uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */
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uint8_t gpi_status_offset; /* specifies offset in struct
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gpi_status */
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@ -522,6 +522,9 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
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irqovr = (void *)current;
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current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags);
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/* NMI */
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
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return current;
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}
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