superio/fintek/f81866d: Add support for UART 3/4

Pins for UART 3/4 are by default GPIO pins.
This patch sets the pins in UART mode.
Since UART 1/3 and 2/4 share the same interrupt line,
the patch needs to enable also shared interrupts.
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html

Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15564
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Fabian Kunkel 2016-07-07 15:15:18 +02:00 committed by Martin Roth
parent ae39fc45a8
commit 145796e171
4 changed files with 92 additions and 1 deletions

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@ -16,5 +16,5 @@
## GNU General Public License for more details.
##
ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c
ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c f81866d_uart.c
ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c

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@ -0,0 +1,74 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
* (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
#include "fintek_internal.h"
#include "f81866d.h"
#define LDN_REG 0x07
#define PORT_SELECT_REGISTER 0x27
#define MULTI_FUNC_SEL3_REG 0x29
#define IRQ_SHARE_REGISTER 0xF0
#define FIFO_SEL_MODE 0xF6
/*
* f81866d_uart_init enables all necessary registers for UART 3/4
* Fintek needs to know if pins are used as GPIO or UART pins
* Share interrupt usage needs to be enabled
*/
void f81866d_uart_init(struct device *dev)
{
struct resource *res = find_resource(dev, PNP_IDX_IO0);
u8 tmp;
if (!res) {
printk(BIOS_WARNING, "%s: No UART resource found.\n", __func__);
return;
}
pnp_enter_conf_mode(dev);
// Set Port Select Register (Bit 0) = 0
// before accessing Multi Function Select 3 Register
tmp = pnp_read_config(dev, PORT_SELECT_REGISTER);
pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE);
// Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO
if (dev->path.pnp.device == F81866D_SP3) {
tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30);
}
// Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO
if (dev->path.pnp.device == F81866D_SP4) {
tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0);
}
// Select UART X in LDN register
pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xff);
// Set IRQ trigger mode from active low to high (Bit 3)
tmp = pnp_read_config(dev, FIFO_SEL_MODE);
pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
// Enable share interrupt (Bit 0)
pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
pnp_exit_conf_mode(dev);
}

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@ -23,5 +23,6 @@
#include <device/pnp.h>
void f81866d_hwm_init(struct device *dev);
void f81866d_uart_init(struct device *dev);
#endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */

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@ -40,6 +40,22 @@ static void f81866d_init(struct device *dev)
// Fixing temp sensor read out and init Fan control
f81866d_hwm_init(dev);
break;
case F81866D_SP1:
// Enable Uart1 and IRQ share register
f81866d_uart_init(dev);
break;
case F81866D_SP2:
// Enable Uart2 and IRQ share register
f81866d_uart_init(dev);
break;
case F81866D_SP3:
// Enable Uart3 and IRQ share register
f81866d_uart_init(dev);
break;
case F81866D_SP4:
// Enable Uart4 and IRQ share register
f81866d_uart_init(dev);
break;
}
}