superio/fintek/f81866d: Add support for UART 3/4
Pins for UART 3/4 are by default GPIO pins. This patch sets the pins in UART mode. Since UART 1/3 and 2/4 share the same interrupt line, the patch needs to enable also shared interrupts. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15564 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -16,5 +16,5 @@
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## GNU General Public License for more details.
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##
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ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c
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ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c f81866d_uart.c
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ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c
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@ -0,0 +1,74 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
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* (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include "fintek_internal.h"
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#include "f81866d.h"
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#define LDN_REG 0x07
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#define PORT_SELECT_REGISTER 0x27
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#define MULTI_FUNC_SEL3_REG 0x29
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#define IRQ_SHARE_REGISTER 0xF0
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#define FIFO_SEL_MODE 0xF6
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/*
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* f81866d_uart_init enables all necessary registers for UART 3/4
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* Fintek needs to know if pins are used as GPIO or UART pins
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* Share interrupt usage needs to be enabled
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*/
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void f81866d_uart_init(struct device *dev)
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{
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struct resource *res = find_resource(dev, PNP_IDX_IO0);
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u8 tmp;
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if (!res) {
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printk(BIOS_WARNING, "%s: No UART resource found.\n", __func__);
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return;
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}
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pnp_enter_conf_mode(dev);
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// Set Port Select Register (Bit 0) = 0
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// before accessing Multi Function Select 3 Register
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tmp = pnp_read_config(dev, PORT_SELECT_REGISTER);
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pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE);
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// Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO
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if (dev->path.pnp.device == F81866D_SP3) {
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tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
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pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30);
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}
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// Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO
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if (dev->path.pnp.device == F81866D_SP4) {
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tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
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pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0);
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}
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// Select UART X in LDN register
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pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xff);
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// Set IRQ trigger mode from active low to high (Bit 3)
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tmp = pnp_read_config(dev, FIFO_SEL_MODE);
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pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
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// Enable share interrupt (Bit 0)
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pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
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pnp_exit_conf_mode(dev);
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}
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@ -23,5 +23,6 @@
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#include <device/pnp.h>
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void f81866d_hwm_init(struct device *dev);
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void f81866d_uart_init(struct device *dev);
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#endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */
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@ -40,6 +40,22 @@ static void f81866d_init(struct device *dev)
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// Fixing temp sensor read out and init Fan control
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f81866d_hwm_init(dev);
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break;
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case F81866D_SP1:
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// Enable Uart1 and IRQ share register
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f81866d_uart_init(dev);
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break;
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case F81866D_SP2:
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// Enable Uart2 and IRQ share register
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f81866d_uart_init(dev);
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break;
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case F81866D_SP3:
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// Enable Uart3 and IRQ share register
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f81866d_uart_init(dev);
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break;
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case F81866D_SP4:
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// Enable Uart4 and IRQ share register
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f81866d_uart_init(dev);
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break;
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}
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}
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