mainboard/lenovo/g505s: Toggle on IOMMU support
Toggle on in devicetree.cb and build into AGESA by buildOpts.c. Add ACPI and MPTABLES interrupt routers for IOMMU also. Change-Id: Ia838f9b70f09ed1180daeb5382edc08c4b74946c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7643 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -22,6 +22,11 @@
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Name(PR0, Package(){
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Name(PR0, Package(){
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/* NB devices */
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/* NB devices */
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/* Bus 0, Dev 0 - F15 Host Controller */
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/* Bus 0, Dev 0 - F15 Host Controller */
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Package(){0x0000FFFF, 0, INTA, 0 },
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Package(){0x0000FFFF, 1, INTB, 0 },
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Package(){0x0000FFFF, 2, INTC, 0 },
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Package(){0x0000FFFF, 3, INTD, 0 },
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
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Package(){0x0001FFFF, 0, INTB, 0 },
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Package(){0x0001FFFF, 0, INTB, 0 },
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Package(){0x0001FFFF, 1, INTC, 0 },
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Package(){0x0001FFFF, 1, INTC, 0 },
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@ -186,7 +186,7 @@
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#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
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#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
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#endif
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#endif
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#define BLDCFG_IOMMU_SUPPORT FALSE
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#define BLDCFG_IOMMU_SUPPORT TRUE
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#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
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#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
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//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
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//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
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@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15rl/root_complex
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chip northbridge/amd/agesa/family15rl # PCI side of HT root complex
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chip northbridge/amd/agesa/family15rl # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
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device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
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device pci 1.1 on end # Internal Multimedia
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device pci 1.1 on end # Internal Multimedia
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device pci 2.0 off end
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device pci 2.0 off end
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@ -118,6 +118,12 @@ static void *smp_write_config_table(void *v)
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#define PCI_INT(bus, dev, int_sign, pin) \
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#define PCI_INT(bus, dev, int_sign, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
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/* IOMMU */
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PCI_INT(0x0, 0x00, 0x0, 0x10);
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PCI_INT(0x0, 0x00, 0x1, 0x11);
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PCI_INT(0x0, 0x00, 0x2, 0x12);
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PCI_INT(0x0, 0x00, 0x3, 0x13);
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/* Internal VGA */
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/* Internal VGA */
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PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
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PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
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PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
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