From 14612f698c1ec76555ebe4c89ca771795450dff1 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Mon, 7 Nov 2022 07:50:51 +0100 Subject: [PATCH] soc/intel/elkhartlake: Correct I2C base clock to 100 MHz According to measurements Elkhart Lake seems to drive the internal I2C controllers with 100 MHz instead of the common 133 MHz. The datasheet itself is quite vague on this definition, just one place mentions that it is 100 MHz (register description for offset 0x94). This patch changes the I2C controller base frequency to 100 MHz. The verification was done by measuring the set up resulting I2C clock for both 100 and 400 kHz. Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Subrata Banik --- src/soc/intel/elkhartlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 4343e85570..8e3dc1196a 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -151,7 +151,7 @@ config CPU_XTAL_HZ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default 133 + default 100 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int