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sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function 

Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47042
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-30 20:21:37 +01:00
parent a7174b7c1d
commit 1464a05933
1 changed files with 19 additions and 19 deletions
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38
src/southbridge/intel/lynxpoint/lpc.c
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@ -70,6 +70,25 @@ static void pch_enable_serial_irqs(struct device *dev)
#endif
}
static void enable_hpet(struct device *const dev)
{
u32 reg32;
size_t i;
/* Assign unique bus/dev/fn for each HPET */
for (i = 0; i < 8; ++i)
pci_write_config16(dev, LPC_HnBDF(i),
PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
/* Move HPET to default address 0xfed00000 and enable it */
reg32 = RCBA32(HPTC);
reg32 |= (1 << 7); // HPET Address Enable
reg32 &= ~(3 << 0);
RCBA32(HPTC) = reg32;
/* Read it back to stick. It's affected by posted write syndrome. */
RCBA32(HPTC);
}
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved
@ -371,25 +390,6 @@ static void lpt_lp_pm_init(struct device *dev)
RCBA32_OR(0x33c8, (1 << 15));
}
static void enable_hpet(struct device *const dev)
{
u32 reg32;
size_t i;
/* Assign unique bus/dev/fn for each HPET */
for (i = 0; i < 8; ++i)
pci_write_config16(dev, LPC_HnBDF(i),
PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
/* Move HPET to default address 0xfed00000 and enable it */
reg32 = RCBA32(HPTC);
reg32 |= (1 << 7); // HPET Address Enable
reg32 &= ~(3 << 0);
RCBA32(HPTC) = reg32;
/* Read it back to stick. It's affected by posted write syndrome. */
RCBA32(HPTC);
}
static void enable_clock_gating(struct device *dev)
{
/* LynxPoint Mobile */