This patch allows support for multiple so-dimms, single or double sided.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -53,7 +53,7 @@ Macros and definitions.
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* 0x2 for Refresh interval 7.8 us for 133MHz
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* 0x2 for Refresh interval 7.8 us for 133MHz
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* 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode)
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* 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode)
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*/
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*/
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#define RAM_COMMAND_REFRESH 0x2
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#define RAM_COMMAND_REFRESH 0x1
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/* DRC[6:4] - SDRAM Mode Select (SMS). */
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/* DRC[6:4] - SDRAM Mode Select (SMS). */
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#define RAM_COMMAND_SELF_REFRESH 0x0
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#define RAM_COMMAND_SELF_REFRESH 0x0
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@ -76,7 +76,7 @@ static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
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uint32_t addr_offset)
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uint32_t addr_offset)
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{
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{
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int i;
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int i;
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uint8_t reg8, reg8_2 = 0;
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uint8_t dimm_start, dimm_end;
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uint32_t reg32;
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uint32_t reg32;
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/* Configure the RAM command. */
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/* Configure the RAM command. */
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@ -84,28 +84,27 @@ static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
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/* Clear bits 29, 10-8, 6-4. */
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/* Clear bits 29, 10-8, 6-4. */
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reg32 &= 0xdffff88f;
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reg32 &= 0xdffff88f;
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reg32 |= command << 4;
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reg32 |= command << 4;
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/* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */
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if (command == RAM_COMMAND_NORMAL)
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reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29));
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pci_write_config32(ctrl->d0, DRC, reg32);
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pci_write_config32(ctrl->d0, DRC, reg32);
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/* RAM_COMMAND_NORMAL affects only the memory controller and
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/* Send the ram command to each row of memory.
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doesn't need to be "sent" to the DIMMs. */
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* (DIMM_SOCKETS * 2) is the maximum number of rows possible.
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/* if (command == RAM_COMMAND_NORMAL) return; */
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* Note: Each DRB defines the upper boundary address of
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* each SDRAM row in 32-MB granularity.
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*/
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dimm_start = 0;
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PRINT_DEBUG(" Sending RAM command 0x");
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for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
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PRINT_DEBUG_HEX32(reg32);
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dimm_end = pci_read_config8(ctrl->d0, DRB + i);
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PRINT_DEBUG(" to 0x");
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if (dimm_end > dimm_start) {
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PRINT_DEBUG_HEX32(0 + addr_offset);
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PRINT_DEBUG(" Sending RAM command 0x");
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PRINT_DEBUG("\r\n");
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PRINT_DEBUG_HEX32(reg32);
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PRINT_DEBUG(" to 0x");
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/* NOTE: Dual-sided ready. */
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PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset);
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read32(0 + addr_offset);
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PRINT_DEBUG("\r\n");
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for (i = 0; i < 4; i++) {
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read32((dimm_start * 32 * 1024 * 1024) + addr_offset);
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reg8 = pci_read_config8(ctrl->d0, DRB + i);
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}
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if (reg8 != reg8_2)
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/* Set the start of the next DIMM. */
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read32(reg8 * 32 * 1024 * 1024);
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dimm_start = dimm_end;
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reg8_2 = reg8;
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}
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}
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}
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}
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@ -316,38 +315,28 @@ static void set_dram_row_attributes(const struct mem_controller *ctrl)
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value = spd_read_byte(device, 5);
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value = spd_read_byte(device, 5);
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if (value == 1) {
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if (value == 1) {
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switch (dra) {
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if (dra == 2) {
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case 2: /* 2KB */
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dra = 0xF0; /* 2KB */
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dra = 0xF0;
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} else if (dra == 4) {
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break;
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dra = 0xF1; /* 4KB */
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case 4: /* 4KB */
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} else if (dra == 8) {
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dra = 0xF1;
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dra = 0xF2; /* 8KB */
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break;
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} else if (dra == 16) {
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case 8: /* 8KB */
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dra = 0xF3; /* 16KB */
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dra = 0xF2;
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} else {
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break;
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case 16: /* 16KB */
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dra = 0xF3;
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break;
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default:
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print_err("Page size not supported\r\n");
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print_err("Page size not supported\r\n");
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die("HALT\r\n");
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die("HALT\r\n");
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}
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}
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} else if (value == 2) {
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} else if (value == 2) {
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switch (dra) {
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if (dra == 2) {
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case 2: /* 2KB */
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dra = 0x00; /* 2KB */
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dra = 0x00;
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} else if (dra == 4) {
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break;
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dra = 0x11; /* 4KB */
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case 4: /* 4KB */
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} else if (dra == 8) {
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dra = 0x11;
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dra = 0x22; /* 8KB */
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break;
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} else if (dra == 16) {
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case 8: /* 8KB */
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dra = 0x33; /* 16KB */
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dra = 0x22;
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} else {
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break;
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case 16: /* 16KB */
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dra = 0x33;
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break;
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default:
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print_err("Page size not supported\r\n");
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print_err("Page size not supported\r\n");
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die("HALT\r\n");
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die("HALT\r\n");
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}
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}
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@ -471,6 +460,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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{
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int i;
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int i;
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uint32_t reg32;
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/* 0. Wait until power/voltages and clocks are stable (200us). */
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/* 0. Wait until power/voltages and clocks are stable (200us). */
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udelay(200);
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udelay(200);
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@ -503,6 +493,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
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do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
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udelay(1);
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udelay(1);
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/* 6. Enable refresh and Set initialization complete. */
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PRINT_DEBUG("RAM Enable 6: Enable Refresh and IC\r\n");
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reg32 = pci_read_config32(ctrl->d0, DRC);
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reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29));
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pci_write_config32(ctrl->d0, DRC, reg32);
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PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
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PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
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DUMPNORTH();
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DUMPNORTH();
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}
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}
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