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Without this patch, if we only got a DIMM in Channel B, memory can not be 

set up correctly. Now it can. Please test it.

Moving "mct_AfterGetCLT(pMCTstat, pDCTstat, dct);" out of the "if" is the
key point.
Changing the Get_DIMMAddress_D(pDCTstat, i) to Get_DIMMAddress_D(pDCTstat, dct + i)
doesnt seem to take any effect. But I believe this is what it should be.

And a duplicated semicolon is removed.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2009-08-25 04:12:55 +00:00 committed by Zheng Bao
parent 4d7ae4d96e
commit 1476a9ecc4
1 changed files with 3 additions and 3 deletions
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6
src/northbridge/amd/amdmct/mct/mct_d.c
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@ -352,7 +352,7 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
nv_DQSTrainCTL = 1;
print_t("DQSTiming_D: mct_BeforeDQSTrain_D:\n");
mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);;
mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
phyAssistedMemFnceTraining(pMCTstat, pDCTstatA);
if (nv_DQSTrainCTL) {
@ -982,8 +982,8 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1;
mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
}
mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
/* Gather all DIMM mini-max values for cycle timing data */
Rows = 0;
@ -1001,7 +1001,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
LDIMM = i >> 1;
if (pDCTstat->DIMMValid & (1 << i)) {
smbaddr = Get_DIMMAddress_D(pDCTstat, i);
smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i);
byte = mctRead_SPD(smbaddr, SPD_ROWSZ);
if (Rows < byte)
Rows = byte; /* keep track of largest row sz */