GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

storm: modify memory layout 

This is an interim change (before EFS is enabled), align ROM and RAM
stages so that they have enough room and do not step over each other.

BUG=chrome-os-partner:27784
TEST=manual
   . booted coreboot successfully on ap148

Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202046
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481
Reviewed-on: http://review.coreboot.org/8012
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This commit is contained in:
Vadim Bendebury 2014-05-28 10:49:51 -07:00 committed by Kyösti Mälkki
parent 2c04117eac
commit 1485c3040b
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/qualcomm/ipq806x/Kconfig
View File

@ -44,11 +44,11 @@ config BOOTBLOCK_BASE
config ROMSTAGE_BASE config ROMSTAGE_BASE
hex hex
default 0x40608000 default 0x40620000
config RAMSTAGE_BASE config RAMSTAGE_BASE
hex hex
default 0x4060c000 default 0x40640000
config SYS_SDRAM_BASE config SYS_SDRAM_BASE
hex hex