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soc/intel/tigerlake: Disable CPU PCIe in FSP 

In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!

BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shaunak Saha 2020-06-18 23:09:11 -07:00 committed by Patrick Georgi
parent 4276050d13
commit 148f8397d2
2 changed files with 7 additions and 0 deletions
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3
src/soc/intel/tigerlake/include/soc/pci_devs.h
View File

@ -34,6 +34,9 @@
#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
#define SA_DEV_SLOT_CPU_PCIE 0x06
#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0)
#define SA_DEV_SLOT_TBT 0x07
#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x))
#define NUM_TBT_FUNCTIONS 4

4
src/soc/intel/tigerlake/romstage/fsp_params.c
View File

@ -217,6 +217,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Skip CPU replacement check */
m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)