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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
1abd667fdf
commit
14a90f1aaf
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@ -3,6 +3,8 @@
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* gwatson@lanl.gov
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*/
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#include <sdram.h>
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extern unsigned _iseg[];
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extern unsigned _liseg[];
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extern unsigned _eliseg[];
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@ -15,7 +17,7 @@ void (*hardwaremain)(int) = _iseg;
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*
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* - turn on real memory
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* - relocate our payload into real memory
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* - start executing payload
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* - start hardwaremain() which does remainder of setup
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*/
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void ppc_main(void)
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@ -0,0 +1,179 @@
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/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*
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*/
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#include <ppc_asm.tmpl>
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#define CACHELINE_SIZE 32 /* 32 bytes (8 words) */
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/*
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* Cache functions.
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*/
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.globl invalidate_icache
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invalidate_icache:
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iccci r0,r0 /* for 405, iccci invalidates the */
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blr /* entire I cache */
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.globl invalidate_dcache
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invalidate_dcache:
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addi r6,0,0x0000 /* clear GPR 6 */
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/* Do loop for # of dcache congruence classes. */
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addi r7,r0, (DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
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/* NOTE: dccci invalidates both */
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mtctr r7 /* ways in the D cache */
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1:
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dccci 0,r6 /* invalidate line */
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addi r6,r6, CACHELINE_SIZE /* bump to next line */
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bdnz 1b
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blr
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.globl flush_dcache
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flush_dcache:
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addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
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ori r9,r9,0x8000
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mfmsr r12 /* save msr */
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andc r9,r12,r9
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mtmsr r9 /* disable EE and CE */
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addi r10,r0,0x0001 /* enable data cache for unused memory */
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mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
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or r10,r10,r9 /* bit 31 in dccr */
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mtdccr r10
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/* do loop for # of congruence classes. */
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addi r10,r0,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
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addi r11,r0,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
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mtctr r10
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addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
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add r11,r10,r11 /* add to get to other side of cache line */
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1:
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lwz r3,0(r10) /* least recently used side */
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lwz r3,0(r11) /* the other side */
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dccci r0,r11 /* invalidate both sides */
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addi r10,r10,CACHELINE_SIZE /* bump to next line */
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addi r11,r11,CACHELINE_SIZE /* bump to next line */
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bdnz 1b
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sync /* allow memory access to complete */
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mtdccr r9 /* restore dccr */
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mtmsr r12 /* restore msr */
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blr
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.globl icache_enable
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icache_enable:
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mflr r8
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bl invalidate_icache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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mticcr r3
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blr
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.globl icache_disable
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icache_disable:
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addis r3,r0, 0x0000 /* clear bit 0 */
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mticcr r3
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isync
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blr
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.globl icache_status
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icache_status:
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mficcr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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.globl dcache_enable
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dcache_enable:
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mflr r8
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bl invalidate_dcache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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mtdccr r3
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blr
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.globl dcache_disable
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dcache_disable:
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mflr r8
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bl flush_dcache
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mtlr r8
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addis r3,r0, 0x0000 /* clear bit 0 */
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mtdccr r3
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blr
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.globl dcache_status
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dcache_status:
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mfdccr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbf */
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/* Description: Data Cache block flush */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbf
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ppcDcbf:
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dcbf r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbi */
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/* Description: Data Cache block Invalidate */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbi
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ppcDcbi:
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dcbi r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcSync */
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/* Description: Processor Synchronize */
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/* Input: none. */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcSync
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ppcSync:
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sync
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blr
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