From 14b444b83be0fe3c3a7fc524265e64d535018049 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 21 Nov 2014 15:54:39 -0800 Subject: [PATCH] arm64: No need of invalidating cache line for secondary CPU stack With support for initializing registers based on values saved by primary CPU, we no longer need to invalidate secondary CPU stack cache lines. Before jumping to C environment, we enable caching and update the required registers. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu. Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82 Signed-off-by: Patrick Georgi Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db Original-Signed-off-by: Furquan Shaikh Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e Original-Reviewed-on: https://chromium-review.googlesource.com/231563 Original-Reviewed-by: Aaron Durbin Original-Tested-by: Furquan Shaikh Original-Commit-Queue: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9541 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/cpu_ramstage.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c index e6d0e8cee2..466ca0124f 100644 --- a/src/arch/arm64/cpu_ramstage.c +++ b/src/arch/arm64/cpu_ramstage.c @@ -151,13 +151,6 @@ static void init_cpu_info(struct bus *bus) } } -static void invalidate_cpu_stack_top(unsigned int id) -{ - const size_t size = 128; - char *stack = cpu_get_stack(id); - dcache_invalidate_by_mva(stack - size, size); -} - void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops) { size_t max_cpus; @@ -221,9 +214,6 @@ void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops) /* Start the CPU. */ printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id); - /* Ensure CPU's top of stack is not in the cache. */ - invalidate_cpu_stack_top(ci->id); - if (cntrl_ops->start_cpu(ci->id, entry)) { printk(BIOS_ERR, "Failed to start CPU%x\n", ci->id);