glados: Enable wake from EC via LAN_WAKE#

Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#.
Report the EC wake pin LAN_WAKE as GPE[112].

BUG=chrome-os-partner:43079
BRANCH=none
TEST=suspend/resume on glados with wake from keyboard

Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288921
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11171
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2015-07-24 15:39:31 -07:00 committed by Aaron Durbin
parent edf1cb78e2
commit 14bb36c5ca
2 changed files with 4 additions and 0 deletions

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@ -29,6 +29,9 @@ Scope (\_SB)
{ {
Return (\_SB.PCI0.LPCB.EC0.LIDS) Return (\_SB.PCI0.LPCB.EC0.LIDS)
} }
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
Name (_PRW, Package(){ 112, 5 }) /* LAN_WAKE_EN */
} }
Device (PWRB) Device (PWRB)

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@ -3,6 +3,7 @@ chip soc/intel/skylake
# Enable deep Sx states # Enable deep Sx states
register "deep_s3_enable" = "1" register "deep_s3_enable" = "1"
register "deep_s5_enable" = "1" register "deep_s5_enable" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
# Must leave UART0 enabled or SD/eMMC will not work as PCI # Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \ register "SerialIoDevMode" = "{ \