mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet BUG=b:193750191 BRANCH=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -125,6 +125,14 @@ chip soc/intel/alderlake
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end
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device ref heci1 on end
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device ref sata on end
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device ref pcie_rp7 on
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# Enable PCIE 7 using clk 6
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register "pch_pcie_rp[PCH_RP(7)]" = "{
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.clk_src = 6,
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.clk_req = 6,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end #PCIE7 RTL8125 Ethernet NIC
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device ref pcie_rp8 on
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# Enable SD Card PCIE 8 using clk 3
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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