intel/cannonlake_rvp: Modify memory parameters to support LP4 board
Replace the support for Cannonlake U DDR4 board to Cannonlake U LPDDR4 platform. TEST=Able to boot up on CNL U LPDDR RVP. Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -36,18 +36,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
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mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
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if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {
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mem_cfg->DqPinsInterleaved = 1;
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mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */
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spd_index = 1;
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} else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */
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mem_cfg->DqPinsInterleaved = 0;
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mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
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mem_cfg->ECT = 1; /* Early Command Training Enabled */
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spd_index = 2;
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}
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printk(BIOS_DEBUG,"SPD INDEX =0x%u\n", spd_index);
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mem_cfg->DqPinsInterleaved = 0;
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mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
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mem_cfg->ECT = 1; /* Early Command Training Enabled */
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spd_index = 2;
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struct region_device spd_rdev;
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@ -31,25 +31,17 @@ void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
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void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
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{
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/* DQ byte map Ch1 */
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const u8 dq_map_u[12] = {
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0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
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const u8 dq_map_y[12] = {
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const u8 dq_map[12] = {
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0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
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if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
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memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u));
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else
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memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y));
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memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
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}
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void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
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{
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/* DQS CPU<>DRAM map Ch0 */
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const u8 dqs_map_u[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };
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const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
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const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
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@ -62,7 +54,7 @@ void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
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void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
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{
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/* DQS CPU<>DRAM map Ch1 */
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const u8 dqs_map_u[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };
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const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
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const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
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@ -82,16 +74,8 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
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void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
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{
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/* Rcomp target */
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static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = {
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100, 33, 32, 33, 28 };
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static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = {
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static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
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80, 40, 40, 40, 30 };
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if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
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memcpy(rcomp_strength_ptr, RcompTarget_U,
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sizeof(RcompTarget_U));
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else
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memcpy(rcomp_strength_ptr, RcompTarget_Y,
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sizeof(RcompTarget_Y));
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memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
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}
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