diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c
index ba453cdb27..8ccd2783c7 100644
--- a/src/soc/intel/broadwell/gma.c
+++ b/src/soc/intel/broadwell/gma.c
@@ -281,7 +281,7 @@ int gtt_poll(u32 reg, u32 mask, u32 value)
 	return 0;
 }
 
-static void igd_setup_panel(struct device *dev)
+static void gma_setup_panel(struct device *dev)
 {
 	config_t *conf = config_of(dev);
 	u32 reg32;
@@ -326,7 +326,8 @@ static void igd_setup_panel(struct device *dev)
 		   Reference clock is 24MHz. We can choose either a 16
 		   or a 128 step increment. Use 16 if we would have less
 		   than 100 steps otherwise. */
-		const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
+		const unsigned int refclock = 24 * MHz;
+		const unsigned int hz_limit = refclock / 128 / 100;
 		unsigned int pwm_increment, pwm_period;
 		u32 south_chicken2;
 
@@ -340,7 +341,12 @@ static void igd_setup_panel(struct device *dev)
 		}
 		gtt_write(SOUTH_CHICKEN2, south_chicken2);
 
-		pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
+		pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
+		printk(BIOS_INFO,
+			"GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n",
+			refclock / MHz, pwm_increment, pwm_period,
+			DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period));
+
 		/* Start with a 50% duty cycle. */
 		gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
 
@@ -532,7 +538,7 @@ static void igd_init(struct device *dev)
 	gtt_write(0xa008, rp1_gfx_freq << 24);
 
 	/* Post VBIOS panel setup */
-	igd_setup_panel(dev);
+	gma_setup_panel(dev);
 
 	/* Initialize PCI device, load/execute BIOS Option ROM */
 	pci_dev_init(dev);