MAINTAINERS: Make Misc Fixes

- X86 architecture is maintained, so mark it as such.
- Legacy AMD chips are supported for odd fixes.
- Remove maintainers whose emails are bouncing.
- Remove maintainers who don't have +2 rights in gerrit.
- According to the instructions, we should use S: Orphan, not Orphaned.
- Update incorrect email addresses.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Martin Roth 2022-10-22 20:34:41 -06:00 committed by Felix Singer
parent b10578a404
commit 14cedd97a5
1 changed files with 4 additions and 5 deletions

View File

@ -665,6 +665,7 @@ F: src/mainboard/sifive/
F: util/riscv/ F: util/riscv/
X86 ARCHITECTURE X86 ARCHITECTURE
S: MAINTAINED
F: src/arch/x86/ F: src/arch/x86/
F: src/cpu/x86/ F: src/cpu/x86/
F: src/drivers/pc80/ F: src/drivers/pc80/
@ -740,6 +741,7 @@ F: src/northbridge/intel/x4x/
AMD SUPPORT AMD SUPPORT
L: amd_coreboot_org_changes@googlegroups.com L: amd_coreboot_org_changes@googlegroups.com
S: Odd Fixes
F: src/vendorcode/amd/ F: src/vendorcode/amd/
F: src/cpu/amd/ F: src/cpu/amd/
F: src/northbridge/amd/ F: src/northbridge/amd/
@ -757,9 +759,7 @@ F: src/drivers/intel/
F: src/include/cpu/intel/ F: src/include/cpu/intel/
INTEL FSP 1.1 INTEL FSP 1.1
M: Lee Leahy <leroy.p.leahy@intel.com>
M: Huang Jin <huang.jin@intel.com> M: Huang Jin <huang.jin@intel.com>
M: York Yang <york.yang@intel.com>
S: Supported S: Supported
F: src/drivers/intel/fsp1_1/ F: src/drivers/intel/fsp1_1/
@ -877,7 +877,6 @@ F: src/soc/intel/tigerlake/
INTEL Xeon Sacalable Processor Family INTEL Xeon Sacalable Processor Family
M: Jonathan Zhang <jonzhang@fb.com> M: Jonathan Zhang <jonzhang@fb.com>
M: Reddy Chagam <anjaneya.chagam@intel.com>
M: Johnny Lin <Johnny_Lin@wiwynn.com> M: Johnny Lin <Johnny_Lin@wiwynn.com>
M: Tim Chu <Tim.Chu@quantatw.com> M: Tim Chu <Tim.Chu@quantatw.com>
M: Arthur Heymans <arthur@aheymans.xyz> M: Arthur Heymans <arthur@aheymans.xyz>
@ -899,7 +898,7 @@ F: src/soc/mediatek/mt8192/
F: src/vendorcode/mediatek/mt8192/ F: src/vendorcode/mediatek/mt8192/
ORPHANED ARM SOCS ORPHANED ARM SOCS
S: Orphaned S: Orphan
F: src/cpu/armltd/ F: src/cpu/armltd/
F: src/soc/ti/ F: src/soc/ti/
F: src/soc/qualcomm/ F: src/soc/qualcomm/
@ -1153,7 +1152,7 @@ MISSING: SPI
CODE OF CONDUCT CODE OF CONDUCT
M: Stefan Reinauer <stefan.reinauer@coreboot.org> M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Ronald Minnich <rminnich@coreboot.org> M: Ronald Minnich <rminnich@gmail.com>
M: Martin Roth <martin@coreboot.org> M: Martin Roth <martin@coreboot.org>
S: Maintained S: Maintained
F: Documentation/community/code_of_conduct.md F: Documentation/community/code_of_conduct.md