MAINTAINERS: Make Misc Fixes
- X86 architecture is maintained, so mark it as such. - Legacy AMD chips are supported for odd fixes. - Remove maintainers whose emails are bouncing. - Remove maintainers who don't have +2 rights in gerrit. - According to the instructions, we should use S: Orphan, not Orphaned. - Update incorrect email addresses. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
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@ -665,6 +665,7 @@ F: src/mainboard/sifive/
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F: util/riscv/
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F: util/riscv/
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X86 ARCHITECTURE
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X86 ARCHITECTURE
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S: MAINTAINED
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F: src/arch/x86/
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F: src/arch/x86/
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F: src/cpu/x86/
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F: src/cpu/x86/
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F: src/drivers/pc80/
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F: src/drivers/pc80/
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@ -740,6 +741,7 @@ F: src/northbridge/intel/x4x/
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AMD SUPPORT
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AMD SUPPORT
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L: amd_coreboot_org_changes@googlegroups.com
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L: amd_coreboot_org_changes@googlegroups.com
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S: Odd Fixes
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F: src/vendorcode/amd/
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F: src/vendorcode/amd/
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F: src/cpu/amd/
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F: src/cpu/amd/
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F: src/northbridge/amd/
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F: src/northbridge/amd/
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@ -757,9 +759,7 @@ F: src/drivers/intel/
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F: src/include/cpu/intel/
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F: src/include/cpu/intel/
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INTEL FSP 1.1
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INTEL FSP 1.1
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M: Lee Leahy <leroy.p.leahy@intel.com>
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M: Huang Jin <huang.jin@intel.com>
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M: Huang Jin <huang.jin@intel.com>
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M: York Yang <york.yang@intel.com>
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S: Supported
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S: Supported
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F: src/drivers/intel/fsp1_1/
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F: src/drivers/intel/fsp1_1/
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@ -877,7 +877,6 @@ F: src/soc/intel/tigerlake/
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INTEL Xeon Sacalable Processor Family
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INTEL Xeon Sacalable Processor Family
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M: Jonathan Zhang <jonzhang@fb.com>
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M: Jonathan Zhang <jonzhang@fb.com>
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M: Reddy Chagam <anjaneya.chagam@intel.com>
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M: Johnny Lin <Johnny_Lin@wiwynn.com>
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M: Johnny Lin <Johnny_Lin@wiwynn.com>
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M: Tim Chu <Tim.Chu@quantatw.com>
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M: Tim Chu <Tim.Chu@quantatw.com>
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M: Arthur Heymans <arthur@aheymans.xyz>
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M: Arthur Heymans <arthur@aheymans.xyz>
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@ -899,7 +898,7 @@ F: src/soc/mediatek/mt8192/
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F: src/vendorcode/mediatek/mt8192/
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F: src/vendorcode/mediatek/mt8192/
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ORPHANED ARM SOCS
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ORPHANED ARM SOCS
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S: Orphaned
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S: Orphan
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F: src/cpu/armltd/
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F: src/cpu/armltd/
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F: src/soc/ti/
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F: src/soc/ti/
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F: src/soc/qualcomm/
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F: src/soc/qualcomm/
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@ -1153,7 +1152,7 @@ MISSING: SPI
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CODE OF CONDUCT
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CODE OF CONDUCT
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M: Stefan Reinauer <stefan.reinauer@coreboot.org>
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M: Stefan Reinauer <stefan.reinauer@coreboot.org>
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M: Ronald Minnich <rminnich@coreboot.org>
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M: Ronald Minnich <rminnich@gmail.com>
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M: Martin Roth <martin@coreboot.org>
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M: Martin Roth <martin@coreboot.org>
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S: Maintained
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S: Maintained
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F: Documentation/community/code_of_conduct.md
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F: Documentation/community/code_of_conduct.md
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