mb/emulation/qemu-q35: Enable CHROMEOS as an option

Allow Chrome OS to be enabled for this QEMU target.  By default
this does not change anything unless it is selected in the build
configuration, but it makes it possible.

Native VGA init is not forced when Chrome OS is enabled because the
drm-bochs driver does not work with chrome (even the latest upstream
kernel driver with drm atomic support) but it does work with virtio.
The coreboot graphics init needs to match what is selected with qemu
(with -vga std or -vga virtio) which in turn will determine which
kernel driver is used.

A second FMAP is added with both RW-A and RW-B regions which is
required by chromeos.

Recovery mode can be entered by supplying a custom fw_cfg option
when launching qemu: -fw_cfg name=opt/cros/recovery,string=1

Change-Id: I24b4532ea961e68558663292c99d121f0a30ce3b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/emulation/qemu-q35/Kconfig

@@ -11,15 +11,16 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_2048 if !VBOOT
 	select BOARD_ROMSIZE_KB_16384 if VBOOT
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
-	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS
 	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_CHROMEOS
 
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_BOOTBLOCK
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_VBNV_CMOS
-	select VBOOT_NO_BOARD_SUPPORT
+	select VBOOT_NO_BOARD_SUPPORT if !CHROMEOS
 	select GBB_FLAG_DISABLE_LID_SHUTDOWN
 	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
@@ -27,7 +28,8 @@ config VBOOT
 
 config FMDFILE
 	string
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa-16M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab-16M.fmd" if VBOOT_SLOTS_RW_AB
 
 if VBOOT
 

src/mainboard/emulation/qemu-q35/Makefile.inc

@@ -10,3 +10,7 @@ postcar-y += ../qemu-i440fx/exit_car.S
 ramstage-y += ../qemu-i440fx/fw_cfg.c
 ramstage-y += ../qemu-i440fx/memmap.c
 ramstage-y += ../qemu-i440fx/northbridge.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c

src/mainboard/emulation/qemu-q35/chromeos.c

@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include "../qemu-i440fx/fw_cfg.h"
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, 1, "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	return 0;
+}
+
+/*
+ * Enable recovery mode with fw_cfg option to qemu:
+ *   -fw_cfg name=opt/cros/recovery,string=1
+ */
+int get_recovery_mode_switch(void)
+{
+	FWCfgFile f;
+
+	if (!fw_cfg_check_file(&f, "opt/cros/recovery")) {
+		uint8_t rec_mode;
+		if (f.size != 1) {
+			printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size);
+			return 0;
+		}
+		fw_cfg_get(f.select, &rec_mode, f.size);
+		if (rec_mode == '1') {
+			printk(BIOS_INFO, "Recovery is enabled.\n");
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/emulation/qemu-q35/vboot-rwab-16M.fmd

@@ -0,0 +1,28 @@
+FLASH@0xff000000 0x1000000 {
+	SI_BIOS 0x1000000 {
+		RW_SECTION_A 0x1c0000 {
+			VBLOCK_A 0x10000
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 0x40
+		}
+		RW_SECTION_B 0x1c0000 {
+			VBLOCK_B 0x10000
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 0x40
+		}
+		RW_SHARED 0x4000 {
+			SHARED_DATA 0x2000
+			VBLOCK_DEV 0x2000
+		}
+		RW_VPD(PRESERVE) 0x1000
+		RW_LEGACY(CBFS) 0x10000
+		WP_RO {
+			FMAP 0x800
+			RO_FRID 0x40
+			RO_PADDING 0x7c0
+			RO_VPD(PRESERVE) 0x1000
+			GBB 0x1e000
+			COREBOOT(CBFS)
+		}
+	}
+}