soc/intel/icelake: Add alignment check for TSEG base and size

This patch ensures to not set SMRR if TSEG base is not align with TSEG size

Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/icelake/smmrelocate.c

@@ -178,6 +178,13 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	const u32 rmask = ~(4 * KiB - 1);
 
 	smm_region(&tseg_base, &tseg_size);
+
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
+		printk(BIOS_WARNING,
+		     "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
+		return;
+	}
+
 	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
 
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */