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soc/intel/skylake: Add device setting for sata power optimization 

This change provides option in devicetree and feeds the option to
FSP SataPwrOptEnable UPD for power saving purpose

BUG=b:70491485

Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kane Chen 2017-12-27 12:11:23 +08:00 committed by Furquan Shaikh
parent 8e4384d0b4
commit 14e0fa5ee0
2 changed files with 4 additions and 0 deletions
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3
src/soc/intel/skylake/chip.h
View File

@ -542,6 +542,9 @@ struct soc_intel_skylake_config {
/* PCH Trip Temperature */
u8 pch_trip_temp;
/* Enable/Disable Sata power optimization */
u8 SataPwrOptEnable;
};
typedef struct soc_intel_skylake_config config_t;

1
src/soc/intel/skylake/chip_fsp20.c
View File

@ -219,6 +219,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SataEnable = config->EnableSata;
params->SataMode = config->SataMode;
params->SataSpeedLimit = config->SataSpeedLimit;
params->SataPwrOptEnable = config->SataPwrOptEnable;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;