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soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state 

Now that APL does not need pmc_fixup_power_state, this function can be
removed from the PMC common code as well.

BUG=b:110836465

Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-06-26 18:08:49 -07:00
parent 344ed02a74
commit 14e8f20edc
2 changed files with 0 additions and 27 deletions
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3
src/soc/intel/common/block/include/intelblocks/pmclib.h
View File

@ -150,9 +150,6 @@ void pmc_global_reset_enable(bool enable);
*/
void pmc_global_reset_lock(void);
/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */
void pmc_fixup_power_state(void);
/* Returns the power state structure */
struct chipset_power_state *pmc_get_power_state(void);

24
src/soc/intel/common/block/pmc/pmclib.c
View File

@ -385,30 +385,6 @@ static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
return soc_prev_sleep_state(ps, prev_sleep_state);
}
/*
* This function re-writes the gpe0 register values in power state
* cbmem variable. After system wakes from sleep state internal PMC logic
* writes default values in GPE_CFG register which gives a wrong offset to
* calculate the wake reason. So we need to set it again to the routing
* table as per the devicetree.
*/
void pmc_fixup_power_state(void)
{
int i;
struct chipset_power_state *ps;
ps = pmc_get_power_state();
if (ps == NULL)
return;
for (i = 0; i < GPE0_REG_MAX; i++) {
ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));
printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
}
}
void pmc_fill_pm_reg_info(struct chipset_power_state *ps)
{
int i;