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soc/intel/common: Add common reset code 

Move reset support into the Intel common branch.  Prevent breaking of
existing platforms by using a Kconfig value to select use of the common
reset code.

BRANCH=none
BUG=None
TEST=Build and run on Glados

Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2
Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/248301
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/9505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Lee Leahy 2015-02-09 21:16:14 -08:00 committed by Patrick Georgi
parent a32b6b9471
commit 14ecb5434b
3 changed files with 60 additions and 0 deletions
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4
src/soc/intel/common/Kconfig
View File

@ -21,3 +21,7 @@ config MRC_SETTINGS_PROTECT
endif # CACHE_MRC_SETTINGS
endif # HAVE_MRC
config SOC_INTEL_COMMON_RESET
bool
default n

2
src/soc/intel/common/Makefile.inc
View File

@ -2,3 +2,5 @@ ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c

54
src/soc/intel/common/reset.c Normal file
View File

@ -0,0 +1,54 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/hlt.h>
#include <arch/io.h>
#include <reset.h>
/* Reset control port */
#define RST_CNT 0xcf9
#define FULL_RST (1 << 3)
#define RST_CPU (1 << 2)
#define SYS_RST (1 << 1)
void hard_reset(void)
{
/* S0->S5->S0 trip. */
outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
while (1)
hlt();
}
void soft_reset(void)
{
/* PMC_PLTRST# asserted. */
outb(RST_CPU | SYS_RST, RST_CNT);
while (1)
hlt();
}
void cpu_reset(void)
{
/* Sends INIT# to CPU */
outb(RST_CPU, RST_CNT);
while (1)
hlt();
}