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soc/intel/common: Use heci_reset() in the CSE TX and RX flows 

The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is a timeout or malformed
response is received from the CSE. Also, the patch triggers HECI
interface reset if the CSE link state is not ready in the heci_send()
API.

TEST=Verify HECI Interface reset in the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sridhar Siricilla 2022-03-05 10:02:25 +05:30 committed by Felix Held
parent 6836da2e5a
commit 1506b77b60
1 changed files with 6 additions and 1 deletions
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7
src/soc/intel/common/block/cse/cse.c
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@ -458,6 +458,8 @@ heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr)
return CSE_TX_RX_SUCCESS;
}
printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n");
heci_reset();
return CSE_TX_ERR_CSE_NOT_READY;
}
@ -548,7 +550,7 @@ static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen)
ret = recv_one_message(&hdr, p, left, &received);
if (ret) {
printk(BIOS_ERR, "HECI: Failed to receive!\n");
return ret;
goto CSE_RX_ERR_HANDLE;
}
left -= received;
p += received;
@ -563,6 +565,9 @@ static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen)
}
}
CSE_RX_ERR_HANDLE:
printk(BIOS_DEBUG, "HECI: Trigger HECI Reset\n");
heci_reset();
return CSE_RX_ERR_CSE_NOT_READY;
}