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src/northbridge: Capitalize CPU, RAM and ROM 

Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-07-28 21:05:26 +02:00 committed by Martin Roth
parent 585d1a0e7d
commit 15279a9696
26 changed files with 41 additions and 41 deletions
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2
src/northbridge/amd/amdfam10/early_ht.c
View File

@ -41,7 +41,7 @@ static void enumerate_ht_chain(void)
if so, don't need to go through the chain */
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* On most boards this just happens. If a CPU has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/

6
src/northbridge/amd/amdht/h3finit.c
View File

@ -917,7 +917,7 @@ static void lookupComputeAndLoadRoutingTables(sMainData *pDat)
*
* Description:
* Find the total number of cores and update the number of nodes and cores in all cpus.
* Limit cpu config access to installed cpus.
* Limit CPU config access to installed cpus.
*
* Parameters:
* @param[in] sMainData* pDat = our global state, number of nodes discovered.
@ -1357,12 +1357,12 @@ static void regangLinks(sMainData *pDat)
pDat->PortList[i+1].SelRegang = FALSE;
if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU))
continue; /* Only process cpu to cpu links */
continue; /* Only process CPU to CPU links */
for (j = i+2; j < pDat->TotalLinks*2; j += 2)
{
if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) )
continue; /* Only process cpu to cpu links */
continue; /* Only process CPU to CPU links */
if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID)
continue; /* Links must be from the same source */

6
src/northbridge/amd/amdk8/coherent_ht.c
View File

@ -113,7 +113,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval)
static void disable_probes(void)
{
/* disable read/write/fill probes for uniprocessor setup
* they don't make sense if only one cpu is available
* they don't make sense if only one CPU is available
*/
/* Hypetransport Transaction Control Register
@ -1597,7 +1597,7 @@ static void coherent_ht_finalize(unsigned nodes)
}
#endif
/* set up cpu count and node count and enable Limit
/* set up CPU count and node count and enable Limit
* Config Space Range for all available CPUs.
* Also clear non coherent hypertransport bus range
* registers on Hammer A0 revision.
@ -1622,7 +1622,7 @@ static void coherent_ht_finalize(unsigned nodes)
#endif
pci_write_config32(dev, 0x60, val);
/* Only respond to real cpu pci configuration cycles
/* Only respond to real CPU pci configuration cycles
* and optimize the HT settings
*/
val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);

2
src/northbridge/amd/amdk8/early_ht.c
View File

@ -8,7 +8,7 @@ static void enumerate_ht_chain(void)
/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* On most boards this just happens. If a CPU has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/

2
src/northbridge/amd/amdk8/f.h
View File

@ -535,7 +535,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
unsigned needs_reset = 0;
if(sysinfo->nodes == 1) return; // in case only one cpu installed
if(sysinfo->nodes == 1) return; // in case only one CPU installed
for(i=1; i<sysinfo->nodes; i++) {
/* Skip everything if I don't have any memory on this controller */

4
src/northbridge/amd/amdk8/incoherent_ht.c
View File

@ -481,7 +481,7 @@ static int ht_setup_chain(device_t udev, unsigned upos)
#endif
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* On most boards this just happens. If a CPU has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
@ -631,7 +631,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
#endif
{
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* On most boards this just happens. If a CPU has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/

6
src/northbridge/amd/amdk8/raminit.c
View File

@ -859,7 +859,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
}
/* Leave a 64M hole between TOP_MEM and TOP_MEM2
* so I can see my rom chip and other I/O devices.
* so I can see my ROM chip and other I/O devices.
*/
if (tom_k >= 0x003f0000) {
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -1243,7 +1243,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
goto single_channel;
}
/* If the cpu is not capable of doing dual channels don't do dual channels */
/* If the CPU is not capable of doing dual channels don't do dual channels */
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
if (!(nbcap & NBCAP_128Bit)) {
goto single_channel;
@ -2476,7 +2476,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
//FIXME add enable node interleaving here -- yhlu
/*needed?
1. check how many nodes we have , if not all has ram installed get out
1. check how many nodes we have , if not all has RAM installed get out
2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out
4. if all ready enable node_interleaving in f1 0x40..... of every node

4
src/northbridge/amd/amdk8/raminit_f.c
View File

@ -1054,7 +1054,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
}
/* Leave a 64M hole between TOP_MEM and TOP_MEM2
* so I can see my rom chip and other I/O devices.
* so I can see my ROM chip and other I/O devices.
*/
if (tom_k >= 0x003f0000) {
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
@ -1460,7 +1460,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
goto single_channel;
}
/* If the cpu is not capable of doing dual channels don't do dual channels */
/* If the CPU is not capable of doing dual channels don't do dual channels */
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
if (!(nbcap & NBCAP_128Bit)) {
goto single_channel;

2
src/northbridge/amd/gx2/northbridgeinit.c
View File

@ -538,7 +538,7 @@ static void rom_shadow_settings(void)
*
* DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough

4
src/northbridge/amd/lx/northbridge.c
View File

@ -46,7 +46,7 @@
#define WRITE_COMBINE (1<<4)
#define WRITE_SERIALIZE (1<<5)
/* ram has none of this stuff */
/* RAM has none of this stuff */
#define RAM_PROPERTIES (0)
#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
@ -86,7 +86,7 @@ struct msr_defaults {
/* for 180a, for now, we assume VSM will configure it */
/* 180b is left at reset value,a0000-bffff is non-cacheable */
/* 180c, c0000-dffff is set to write serialize and non-cachable */
/* oops, 180c will be set by cpu bug handling in cpubug.c */
/* oops, 180c will be set by CPU bug handling in cpubug.c */
//{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
/* 180d is left at default, e0000-fffff is non-cached */
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */

2
src/northbridge/amd/lx/northbridgeinit.c
View File

@ -591,7 +591,7 @@ static void rom_shadow_settings(void)
*
* DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough

2
src/northbridge/intel/e7501/northbridge.c
View File

@ -69,7 +69,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the limit of the remap window */
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
}
/* Write the ram configuration registers,
/* Write the RAM configuration registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);

2
src/northbridge/intel/e7505/northbridge.c
View File

@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the limit of the remap window */
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
}
/* Write the ram configuration registers,
/* Write the RAM configuration registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, TOLM);

2
src/northbridge/intel/gm45/early_reset.c
View File

@ -64,6 +64,6 @@ void gm45_early_reset(void/*const timings_t *const timings*/)
/* Perform system reset through CF9 interface. */
outb(0x02, 0xcf9); /* Set system reset bit. */
outb(0x06, 0xcf9); /* Set cpu reset bit, too. */
outb(0x06, 0xcf9); /* Set CPU reset bit, too. */
halt();
}

2
src/northbridge/intel/haswell/Kconfig
View File

@ -65,7 +65,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
default 0x2000
help
The amount of anticipated stack usage from the data cache
during pre-ram rom stage execution.
during pre-ram ROM stage execution.
config HAVE_MRC
bool "Add a System Agent binary"

2
src/northbridge/intel/i3100/northbridge.c
View File

@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev)
/* Find the offset of the remap window from tolm */
remapoffsetk = remapbasek - tolmk;
}
/* Write the ram configruation registers,
/* Write the RAM configruation registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);

2
src/northbridge/intel/i3100/raminit.c
View File

@ -603,7 +603,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
long dimm_mask;
/* Test if we can read the spd and if ram is ddr or ddr2 */
/* Test if we can read the spd and if RAM is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
printk(BIOS_ERR, "No memory for this cpu\n");

2
src/northbridge/intel/i855/northbridge.c
View File

@ -87,7 +87,7 @@ static void pci_domain_set_resources(device_t dev)
*/
tolmk = tomk;
}
/* Write the ram configuration registers,
/* Write the RAM configuration registers,
* preserving the reserved bits.
*/

2
src/northbridge/intel/i855/raminit.c
View File

@ -878,7 +878,7 @@ static void spd_update(u8 reg, u32 new_value)
#endif
}
/* if ram still doesn't work do this function */
/* if RAM still doesn't work do this function */
static void spd_set_undocumented_registers(void)
{
spd_update(0x74, 0x00000001);

4
src/northbridge/intel/i945/raminit.c
View File

@ -85,7 +85,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command)
static void ram_read32(u32 offset)
{
PRINTK_DEBUG(" ram read: %08x\n", offset);
PRINTK_DEBUG(" RAM read: %08x\n", offset);
read32((void *)offset);
}
@ -1453,7 +1453,7 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno
val_err:
die("Bad SPD value\n");
hw_err:
/* If a hardware error occurs the spd rom probably does not exist.
/* If a hardware error occurs the spd ROM probably does not exist.
* In this case report that there is no memory
*/
sz.side1 = 0;

4
src/northbridge/intel/sandybridge/raminit.c
View File

@ -1121,7 +1121,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
gfxstolenbase -= tsegbasedelta;
toludbase -= tsegbasedelta;
// Test if it is possible to reclaim a hole in the ram addressing
// Test if it is possible to reclaim a hole in the RAM addressing
if (tom - me_uma_size > toludbase) {
// Reclaim is possible
reclaim = 1;
@ -4080,7 +4080,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
/* Set scheduler parameters */
MCHBAR32(0x4c20) = 0x10100005;
/* Set cpu specific register */
/* Set CPU specific register */
set_4f8c();
/* Clear IO reset bit */

4
src/northbridge/via/cx700/lpc.c
View File

@ -203,7 +203,7 @@ static void cx700_set_lpc_registers(struct device *dev)
enables |= 1 << 3;
pci_write_config8(dev, 0x4d, enables);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
/* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
@ -220,7 +220,7 @@ static void cx700_set_lpc_registers(struct device *dev)
// Power management setup
setup_pm(dev);
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
/* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
/* Enable HPET timer */

8
src/northbridge/via/vx800/lpc.c
View File

@ -269,7 +269,7 @@ static void vx800_sb_init(struct device *dev)
enables |= 0x41; //
pci_write_config8(dev, 0x58, enables);
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
/* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
@ -283,7 +283,7 @@ static void vx800_sb_init(struct device *dev)
// Power management setup
setup_pm(dev);
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
/* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
@ -329,14 +329,14 @@ static void southbridge_init(struct device *dev)
S3_usb_wakeup(dev);
S3_lid_wakeup(dev);
/* enable acpi cpu c3 state. (c2 state need not do anything.)
/* enable acpi CPU c3 state. (c2 state need not do anything.)
#1
fadt->pm2_cnt_blk = 0x22;//to support cpu-c3
fadt->p_lvl2_lat = 0x50; //this is the coreboot source
fadt->p_lvl3_lat = 0x320;//
fadt->pm2_cnt_len = 1;//to support cpu-c3
#2
ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
#3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
1 enable SLP# asserts in C3 state PMIORx26<1> =1
2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1

2
src/northbridge/via/vx800/northbridge.c
View File

@ -70,7 +70,7 @@ static const struct pci_driver memctrl_driver __pci_driver = {
static void pci_domain_set_resources(device_t dev)
{
/*
* the order is important to find the correct ram size.
* the order is important to find the correct RAM size.
*/
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
device_t mc_dev;

2
src/northbridge/via/vx800/uma_ram_setting.c
View File

@ -168,7 +168,7 @@ void SetUMARam(void)
Tmp = VIACONFIG_VGA_PCI_14;
pci_write_config32(vga_dev, 0x14, Tmp);
//enable direct cpu frame buffer access
//enable direct CPU frame buffer access
i = pci_read_config8(PCI_DEV(0, 0, 3), 0xa1);
i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
pci_write_config8(PCI_DEV(0, 0, 3), 0xa1, i);

2
src/northbridge/via/vx900/northbridge.c
View File

@ -259,7 +259,7 @@ static void vx900_set_resources(device_t dev)
tolmk = MIN(full_tolmk, tomk);
tolmk -= fbufk;
ram_resource(dev, idx++, 0, 640);
printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10);
printk(BIOS_SPEW, "System RAM left: %dMB\n", tolmk >> 10);
/* FIXME: how can we avoid leaving this hole?
* Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */
/* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem