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soc/amd: Move SPI base alignment define into common 

The decision to leave the alignment in stoneyridge was driven because
of a spec difference with picasso.  AMD has checked the design
materials and has confirmed there was no change.

TEST=Build Grunt successfully
BUG=b:130343127

Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-07-16 09:37:16 -06:00 committed by Martin Roth
parent 5f7b1164c5
commit 152a5e1916
3 changed files with 1 additions and 6 deletions
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1
src/soc/amd/common/block/include/amdblocks/lpc.h
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@ -114,6 +114,7 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90 #define LPC_WIDEIO2_GENERIC_PORT 0x90
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 #define SPIROM_BASE_ADDRESS_REGISTER 0xa0
#define SPI_BASE_ALIGNMENT BIT(6)
#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) #define SPI_BASE_RESERVED (BIT(4) | BIT(5))
#define ROUTE_TPM_2_SPI BIT(3) #define ROUTE_TPM_2_SPI BIT(3)
#define SPI_ABORT_ENABLE BIT(2) #define SPI_ABORT_ENABLE BIT(2)

3
src/soc/amd/picasso/include/soc/southbridge.h
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@ -225,9 +225,6 @@
#define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITIES_REG 0xfc
#define SATA_CAPABILITY_SPM BIT(12) #define SATA_CAPABILITY_SPM BIT(12)
/* SPI Controller (base address in D14F3xA0) */
#define SPI_BASE_ALIGNMENT BIT(6)
#define SPI_CNTRL0 0x00 #define SPI_CNTRL0 0x00
#define SPI_BUSY BIT(31) #define SPI_BUSY BIT(31)
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))

3
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -254,9 +254,6 @@
#define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITIES_REG 0xfc
#define SATA_CAPABILITY_SPM BIT(12) #define SATA_CAPABILITY_SPM BIT(12)
/* SPI Controller (base address in D14F3xA0) */
#define SPI_BASE_ALIGNMENT BIT(6)
#define SPI_CNTRL0 0x00 #define SPI_CNTRL0 0x00
#define SPI_BUSY BIT(31) #define SPI_BUSY BIT(31)
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))