GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

mb/google/brya/var/mithrax: adjust I2C5 times for TP

Browse source 
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to
follow I2C specification.

I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us.
I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us.

BUG=b:249031186
BRANCH=brya
TEST=EE check OK with test FW and TP function is normal.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
This commit is contained in:
John Su 2022-09-28 10:25:30 +08:00 committed by Martin Roth
parent 4531edf083
commit 153e526f77
1 changed files with 6 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/mainboard/google/brya/variants/mithrax/overridetree.cb
View file

@ -81,7 +81,12 @@ chip soc/intel/alderlake
.speed = I2C_SPEED_FAST,
.rise_time_ns = 550,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 160,
.scl_hcnt = 70,
.sda_hold = 40,
}
},
}"