soc/intel/{cnl,icl,skl}: Fix multiple whitespace issue

Change-Id: I1e3dc1bd36c5de4e58eef6a3ba8ccbde28fba64b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36465
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/bootblock/pch.c

@@ -90,7 +90,7 @@ static void soc_config_pwrmbase(void)
 
 	/* Enable Bus Master and MMIO Space */
 	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 |=  PCI_COMMAND_MEMORY;
+	reg32 |= PCI_COMMAND_MEMORY;
 	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
 
 	/* Enable PWRM in PMC */

src/soc/intel/cannonlake/cpu.c

@@ -399,7 +399,7 @@ static void enable_pm_timer_emulation(void)
 	 * frequency is used.
 	 */
 	msr.hi = (3579545ULL << 32) / CTC_FREQ;
-	/* Set PM1 timer IO port and enable*/
+	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
 	wrmsr(MSR_EMULATE_PM_TIMER, msr);

src/soc/intel/icelake/bootblock/pch.c

@@ -72,7 +72,7 @@ static void soc_config_pwrmbase(void)
 
 	/* Enable Bus Master and MMIO Space */
 	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 |=  PCI_COMMAND_MEMORY;
+	reg32 |= PCI_COMMAND_MEMORY;
 	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
 
 	/* Enable PWRM in PMC */

src/soc/intel/icelake/cpu.c

@@ -127,7 +127,7 @@ static void enable_pm_timer_emulation(void)
 	 * frequency is used.
 	 */
 	msr.hi = (3579545ULL << 32) / CTC_FREQ;
-	/* Set PM1 timer IO port and enable*/
+	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
 	wrmsr(MSR_EMULATE_PM_TIMER, msr);

src/soc/intel/skylake/cpu.c

@@ -414,7 +414,7 @@ static void enable_pm_timer_emulation(void)
 	 * frequency is used.
 	 */
 	msr.hi = (3579545ULL << 32) / CTC_FREQ;
-	/* Set PM1 timer IO port and enable*/
+	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
 	wrmsr(MSR_EMULATE_PM_TIMER, msr);