mb/asus/p5qc: Add mainboard
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS support for ATA. It works fine in Linux afterwards. Working: - SATA on southbridge port - SATA on marvel IDE controller ports (only in Linux) - USB - COM1 - PS2 Keyboard - DDR2 DIMMs - PCIe x16 PEG port - PCI port - NIC (needs a driver to set macaddress) - S3 resume Not working: - SeaBIOS with ATA support (long timeout marvel controller so disabled) - DDR3 fails because the proper clock signal does not get enabled. Even when fixing this it fails later or during memtest, so it should be considered unsupported for now Untested: - PCIe x1 ports (expected to work) - sound (expected to work) TODO: add documentation Change-Id: I4a81940707566776bd048904ca1387fea741fece Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
Felix Held
parent
6db1b2fc24
commit
1541256f22
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@ -0,0 +1,51 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_ASUS_P5QC
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801JX
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select SUPERIO_WINBOND_W83667HG_A
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_1024
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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config MAINBOARD_DIR
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string
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default "asus/p5qc"
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config MAINBOARD_PART_NUMBER
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string
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default "P5QC"
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config MAX_CPUS
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int
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default 4
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# The MARVEL IDE controller delays SeaBIOS a lot and results in an unbootable
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# bogus disk. Compiling SeaBIOS without ATA support is a workaround.
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config PAYLOAD_CONFIGFILE
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string
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default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS
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endif # BOARD_ASUS_P5QC
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@ -0,0 +1,2 @@
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config BOARD_ASUS_P5QC
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bool "P5QC"
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@ -0,0 +1,15 @@
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#
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# This file is part of the coreboot project.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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ramstage-y += cstates.c
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romstage-y += gpio.c
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/* dummy */
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This is board specific information:
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* IRQ routing for the 0:1e.0 PCI bridge of the ICH10
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*/
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If (PICM) {
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Return (Package() {
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/* PCI slot */
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Package() { 0x0000ffff, 0, 0, 0x10},
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Package() { 0x0000ffff, 1, 0, 0x11},
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Package() { 0x0000ffff, 2, 0, 0x12},
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Package() { 0x0000ffff, 3, 0, 0x13},
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Package() { 0x0001ffff, 0, 0, 0x11},
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Package() { 0x0001ffff, 1, 0, 0x12},
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Package() { 0x0001ffff, 2, 0, 0x13},
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Package() { 0x0001ffff, 3, 0, 0x10},
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Package() { 0x0002ffff, 0, 0, 0x12},
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Package() { 0x0002ffff, 1, 0, 0x13},
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Package() { 0x0002ffff, 2, 0, 0x10},
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Package() { 0x0002ffff, 3, 0, 0x11},
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Package() { 0x0003ffff, 0, 0, 0x13},
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
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Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
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Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
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Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
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Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
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Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
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Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
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Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
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})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_PIC, 1)
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{
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/* Remember the OS' IRQ routing choice. */
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Store(Arg0, PICM)
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}
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/* SMI I/O Trap */
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Method(TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) /* SMI Function */
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Store (0, TRP0) /* Generate trap */
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Return (SMIF) /* Return value of SMI handler */
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}
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/* TODO */
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <southbridge/intel/i82801jx/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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memset((void *)gnvs, 0, sizeof(*gnvs));
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gnvs->pwrs = 1; /* Power state (AC = 1) */
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gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
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gnvs->apic = 1; /* Enable APIC */
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gnvs->mpen = 1; /* Enable Multi Processing */
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gnvs->cmap = 0x01; /* Enable COM 1 port */
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}
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Category: desktop
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Board URL: https://www.asus.com/Motherboards/P5QC/
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ROM package: SOP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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boot_option=Fallback
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debug_level=Spew
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power_on_after_fail=Disable
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nmi=Enable
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sata_mode=AHCI
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 5 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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# coreboot config options: southbridge
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408 1 e 10 sata_mode
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409 2 e 7 power_on_after_fail
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411 1 e 1 nmi
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# coreboot config options: cpu
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#424 8 r 0 unused
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# coreboot config options: northbridge
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#432 554 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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1024 144 r 0 recv_enable_results
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# -----------------------------------------------------------------
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enumerations
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|
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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10 0 AHCI
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10 1 Compatible
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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# CONFIG_ATA is not set
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/*
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* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpigen.h>
|
||||
#include <device/device.h>
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
|
||||
int get_cst_entries(acpi_cstate_t **entries)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
|
||||
# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
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chip northbridge/intel/x4x # Northbridge
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_LGA775
|
||||
device lapic 0 on end
|
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end
|
||||
chip cpu/intel/model_1067x # CPU
|
||||
device lapic 0xACAC off end
|
||||
end
|
||||
end
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host Bridge
|
||||
device pci 1.0 on end # PEG
|
||||
device pci 2.0 off end # Integrated graphics controller
|
||||
device pci 2.1 off end # Integrated graphics controller 2
|
||||
device pci 3.0 off end # ME
|
||||
device pci 3.1 off end # ME
|
||||
device pci 3.2 off end # ME
|
||||
device pci 3.3 off end # ME
|
||||
device pci 6.0 off end # PEG 2
|
||||
chip southbridge/intel/i82801jx # Southbridge
|
||||
register "gpe0_en" = "0x40"
|
||||
|
||||
# Set AHCI mode.
|
||||
register "sata_port_map" = "0x3f"
|
||||
register "sata_clock_request" = "0"
|
||||
register "sata_traffic_monitor" = "0"
|
||||
|
||||
# Enable PCIe ports 0,2,3 as slots.
|
||||
register "pcie_slot_implemented" = "0x31"
|
||||
|
||||
device pci 19.0 off end # GBE
|
||||
device pci 1a.0 on end # USB
|
||||
device pci 1a.1 on end # USB
|
||||
device pci 1a.2 on end # USB
|
||||
device pci 1a.7 on end # USB
|
||||
device pci 1b.0 on end # Audio
|
||||
device pci 1c.0 on end # PCIe 1
|
||||
device pci 1c.1 off end # PCIe 2
|
||||
device pci 1c.2 off end # PCIe 3
|
||||
device pci 1c.3 off end # PCIe 4
|
||||
device pci 1c.4 on end # PCIe 5 MARVEL IDE
|
||||
device pci 1c.5 on end # PCIe 6
|
||||
device pci 1d.0 on end # USB
|
||||
device pci 1d.1 on end # USB
|
||||
device pci 1d.2 on end # USB
|
||||
device pci 1d.7 on end # USB
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/winbond/w83667hg-a # Super I/O
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 off end # LPT1
|
||||
device pnp 2e.2 on # COM1
|
||||
# Global registers
|
||||
irq 0x2a = 0x00
|
||||
irq 0x2c = 0x22
|
||||
irq 0x2d = 0x00
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off end # COM2
|
||||
device pnp 2e.5 on # PS/2 keyboard & mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.106 off end # SPI1
|
||||
device pnp 2e.107 off end # GIPO6
|
||||
device pnp 2e.207 off end # GIPO7
|
||||
device pnp 2e.307 on # GIPO8
|
||||
irq 0xe4 = 0xfb
|
||||
irq 0xe5 = 0x02
|
||||
end
|
||||
device pnp 2e.407 off end # GIPO9
|
||||
device pnp 2e.8 off end # WDT
|
||||
device pnp 2e.108 off end # GPIO 1
|
||||
device pnp 2e.9 off end # GPIO2
|
||||
device pnp 2e.109 on end # GPIO3
|
||||
device pnp 2e.209 on # GPIO4
|
||||
irq 0xf0 = 0x7f
|
||||
irq 0xfe = 0x07
|
||||
end
|
||||
device pnp 2e.309 on end # GPIO5
|
||||
device pnp 2e.a on # ACPI
|
||||
irq 0xe4 = 0x10 # 3VSBSW# enable
|
||||
irq 0xe5 = 0x02
|
||||
irq 0xf2 = 0xfc
|
||||
end
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 0
|
||||
# IRQ purposefully not assigned to prevent lockups
|
||||
end
|
||||
device pnp 2e.c on end # PECI
|
||||
device pnp 2e.d on end # VID_BUSSEL
|
||||
device pnp 2e.f on end # GPIO_PP_OD
|
||||
end
|
||||
end
|
||||
device pci 1f.1 off end # PATA/IDE
|
||||
device pci 1f.2 on end # SATA
|
||||
device pci 1f.3 on end # SMbus
|
||||
device pci 1f.4 off end
|
||||
device pci 1f.5 off end # IDE
|
||||
device pci 1f.6 off end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x00000001 // OEM revision
|
||||
)
|
||||
{
|
||||
// global NVS and variables
|
||||
#include "acpi/platform.asl"
|
||||
#include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/x4x/acpi/x4x.asl>
|
||||
#include <southbridge/intel/i82801jx/acpi/ich10.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/i82801jx/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio10 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_GPIO,
|
||||
.gpio19 = GPIO_MODE_GPIO,
|
||||
.gpio20 = GPIO_MODE_GPIO,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_GPIO,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio10 = GPIO_DIR_INPUT,
|
||||
.gpio12 = GPIO_DIR_INPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio18 = GPIO_DIR_INPUT,
|
||||
.gpio19 = GPIO_DIR_INPUT,
|
||||
.gpio20 = GPIO_DIR_OUTPUT,
|
||||
.gpio21 = GPIO_DIR_OUTPUT,
|
||||
.gpio22 = GPIO_DIR_INPUT,
|
||||
.gpio23 = GPIO_DIR_OUTPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio20 = GPIO_LEVEL_HIGH,
|
||||
.gpio21 = GPIO_LEVEL_HIGH,
|
||||
.gpio23 = GPIO_LEVEL_HIGH,
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio27 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio7 = GPIO_INVERT,
|
||||
.gpio10 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio56 = GPIO_MODE_GPIO,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_OUTPUT,
|
||||
.gpio35 = GPIO_DIR_OUTPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_OUTPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_OUTPUT,
|
||||
.gpio48 = GPIO_DIR_OUTPUT,
|
||||
.gpio49 = GPIO_DIR_OUTPUT,
|
||||
.gpio56 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio34 = GPIO_LEVEL_LOW,
|
||||
.gpio35 = GPIO_LEVEL_LOW,
|
||||
.gpio37 = GPIO_LEVEL_LOW,
|
||||
.gpio39 = GPIO_LEVEL_HIGH,
|
||||
.gpio48 = GPIO_LEVEL_LOW,
|
||||
.gpio49 = GPIO_LEVEL_HIGH,
|
||||
.gpio57 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0888,
|
||||
0x104382fe, // Subsystem ID
|
||||
13, // Number of entries
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x11, 0x99430140),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x01011012),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x01016011),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x01012014),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19d60),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02214d20),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x01447130),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
|
||||
const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <cpu/x86/bist.h>
|
||||
#include <cpu/intel/romstage.h>
|
||||
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
#include <lib.h>
|
||||
#include <northbridge/intel/x4x/iomap.h>
|
||||
#include <timestamp.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
|
||||
/* Early mainboard specific GPIO setup.
|
||||
* We should use standard gpio.h eventually
|
||||
*/
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Set the value for GPIO base address register and enable GPIO. */
|
||||
pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));
|
||||
pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);
|
||||
|
||||
setup_pch_gpios(&mainboard_gpio_map);
|
||||
|
||||
/* Set default GPIOs on superio: TODO (here or in ramstage) */
|
||||
|
||||
/* Enable IOAPIC */
|
||||
RCBA8(0x31ff) = 0x03;
|
||||
RCBA8(0x31ff);
|
||||
|
||||
/* TODO? */
|
||||
RCBA32(RCBA_CG) = 0xbf7f001f;
|
||||
RCBA32(0x3430) = 0x00000002;
|
||||
RCBA32(0x3f00) = 0x00000038;
|
||||
}
|
||||
|
||||
static void ich10_enable_lpc(void)
|
||||
{
|
||||
/* Configure serial IRQs.*/
|
||||
pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
|
||||
pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
|
||||
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
|
||||
| COMA_LPC_EN);
|
||||
/* HW EC */
|
||||
pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);
|
||||
/* ????? */
|
||||
pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701);
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(unsigned long bist)
|
||||
{
|
||||
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
|
||||
u8 boot_path = 0;
|
||||
u8 s3_resume;
|
||||
|
||||
timestamp_init(get_initial_timestamp());
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
|
||||
/* Set southbridge and Super I/O GPIOs. */
|
||||
ich10_enable_lpc();
|
||||
mb_gpio_init();
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
report_bist_failure(bist);
|
||||
enable_smbus();
|
||||
|
||||
x4x_early_init();
|
||||
|
||||
s3_resume = southbridge_detect_s3_resume();
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
printk(BIOS_DEBUG, "Initializing memory\n");
|
||||
timestamp_add_now(TS_BEFORE_INITRAM);
|
||||
sdram_initialize(boot_path, spd_addrmap);
|
||||
timestamp_add_now(TS_AFTER_INITRAM);
|
||||
quick_ram_check();
|
||||
printk(BIOS_DEBUG, "Memory initialized\n");
|
||||
|
||||
x4x_late_init(s3_resume);
|
||||
|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
}
|
||||
Loading…
Reference in New Issue