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intel PCI ops: Remove explicit PCI MMCONF access 

MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

I liked the style of code in pci_mmio_cfg.h more, and used those to
replace the ones in io.h.

Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17689
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2013-07-26 08:53:59 +03:00
parent 8db31a8f4e
commit 154768b902
6 changed files with 51 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
src/arch/x86/include/arch/io.h
View File

@ -246,24 +246,6 @@ typedef u32 device_t;
#include <arch/pci_io_cfg.h>
#include <arch/pci_mmio_cfg.h>
static inline __attribute__((always_inline))
void pci_or_config8(pci_devfn_t dev, unsigned where, uint8_t value)
{
pci_write_config8(dev, where, pci_read_config8(dev, where) | value);
}
static inline __attribute__((always_inline))
void pci_or_config16(pci_devfn_t dev, unsigned where, uint16_t value)
{
pci_write_config16(dev, where, pci_read_config16(dev, where) | value);
}
static inline __attribute__((always_inline))
void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value)
{
pci_write_config32(dev, where, pci_read_config32(dev, where) | value);
}
#define PCI_DEV_INVALID (0xffffffffU)
static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev)
{
@ -367,4 +349,29 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned index, unsigned drq)
#endif /* __SIMPLE_DEVICE__ */
#ifndef __SIMPLE_DEVICE__
#include <device/pci_ops.h>
#endif
static inline __attribute__ ((always_inline))
void pci_or_config8(device_t dev, unsigned int where, u8 ormask)
{
u8 value = pci_read_config8(dev, where);
pci_write_config8(dev, where, value | ormask);
}
static inline __attribute__ ((always_inline))
void pci_or_config16(device_t dev, unsigned int where, u16 ormask)
{
u16 value = pci_read_config16(dev, where);
pci_write_config16(dev, where, value | ormask);
}
static inline __attribute__ ((always_inline))
void pci_or_config32(device_t dev, unsigned int where, u32 ormask)
{
u32 value = pci_read_config32(dev, where);
pci_write_config32(dev, where, value | ormask);
}
#endif

21
src/arch/x86/include/arch/pci_mmio_cfg.h
View File

@ -69,27 +69,6 @@ void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
write32(addr, value);
}
static inline __attribute__ ((always_inline))
void pcie_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask)
{
u8 value = pcie_read_config8(dev, where);
pcie_write_config8(dev, where, value | ormask);
}
static inline __attribute__ ((always_inline))
void pcie_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask)
{
u16 value = pcie_read_config16(dev, where);
pcie_write_config16(dev, where, value | ormask);
}
static inline __attribute__ ((always_inline))
void pcie_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask)
{
u32 value = pcie_read_config32(dev, where);
pcie_write_config32(dev, where, value | ormask);
}
#define pci_mmio_read_config8 pcie_read_config8
#define pci_mmio_read_config16 pcie_read_config16
#define pci_mmio_read_config32 pcie_read_config32

22
src/northbridge/intel/fsp_sandybridge/finalize.c
View File

@ -22,17 +22,17 @@
void intel_sandybridge_finalize_smm(void)
{
pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */

22
src/northbridge/intel/nehalem/finalize.c
View File

@ -22,17 +22,17 @@
void intel_nehalem_finalize_smm(void)
{
pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */

4
src/southbridge/intel/fsp_bd82x6x/finalize.c
View File

@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void)
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */
pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);

4
src/southbridge/intel/fsp_i89xx/finalize.c
View File

@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void)
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */
pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);