Various minor cosmetic changes in the ITE Super I/Os, mostly whitespace
changes and fixing of comments. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
faea4c59ab
commit
1549f2a557
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@ -20,3 +20,4 @@
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config chip.h
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object superio.o
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@ -23,14 +23,12 @@
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/* This chip doesn't seem to have keyboard and mouse support. */
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/* #include <pc80/keyboard.h> */
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#include <uart8250.h>
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extern struct chip_operations superio_ite_it8661f_ops;
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struct superio_ite_it8661f_config {
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struct uart8250 com1, com2;
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/* struct pc_keyboard keyboard; */
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};
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#endif /* _SUPERIO_ITE_IT8661F */
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@ -19,7 +19,7 @@
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*/
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/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */
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/* Status: untested on real hardware, but it compiles. */
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/* Status: Untested on real hardware, but it compiles. */
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/* This chip doesn't seem to have keyboard and mouse support. */
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@ -26,7 +26,7 @@
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA SIO_BASE+1
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/* Global Configuration Registers. */
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/* Global configuration registers. */
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#define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8661F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8661F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
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@ -35,7 +35,7 @@
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#define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
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/* Special values used for entering MB PnP mode. The first four bytes of
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* each line determine the address port, the last four are data. */
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each line determine the address port, the last four are data. */
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static const uint8_t init_values[] = {
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0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
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0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
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@ -44,7 +44,7 @@ static const uint8_t init_values[] = {
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};
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/* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the
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* LDN the register belongs to, before you can access the register. */
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LDN the register belongs to, before you can access the register. */
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static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
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{
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outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
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@ -53,7 +53,7 @@ static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
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outb(value, SIO_DATA);
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}
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/* Enable the peripheral devices on the IT8661F Super IO chip. */
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/* Enable the peripheral devices on the IT8661F Super I/O chip. */
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static void it8661f_enable_serial(device_t dev, unsigned iobase)
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{
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uint8_t i;
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@ -88,10 +88,10 @@ static void it8661f_enable_serial(device_t dev, unsigned iobase)
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it8661f_sio_write(IT8661F_IR, 0x30, 0x1); /* IR */
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/* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
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(clear bit 0). */
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(clear bit 0). */
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it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00);
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/* (3) Exit the configuration state (MB PnP mode). */
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it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02);
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it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02);
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}
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@ -20,3 +20,4 @@
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config chip.h
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object superio.o
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@ -26,7 +26,7 @@
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA SIO_BASE+1
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/* Global Configuration Registers. */
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/* Global configuration registers. */
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#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
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@ -35,7 +35,7 @@
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#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
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/* Special values used for entering MB PnP mode. The first four bytes of
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* each line determine the address port, the last four are data. */
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each line determine the address port, the last four are data. */
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static const uint8_t init_values[] = {
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0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
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0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
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@ -44,7 +44,7 @@ static const uint8_t init_values[] = {
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};
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/* The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the
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* LDN the register belongs to, before you can access the register. */
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LDN the register belongs to, before you can access the register. */
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static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
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{
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outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
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@ -53,7 +53,7 @@ static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
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outb(value, SIO_DATA);
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}
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/* Enable the peripheral devices on the IT8671F Super IO chip. */
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/* Enable the peripheral devices on the IT8671F Super I/O chip. */
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static void it8671f_enable_serial(device_t dev, unsigned iobase)
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{
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uint8_t i;
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@ -80,7 +80,7 @@ static void it8671f_enable_serial(device_t dev, unsigned iobase)
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PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
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it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
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/* Activate all devices. */
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/* Activate all devices. */
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it8671f_sio_write(IT8671F_FDC, 0x30, 0x01); /* Floppy */
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it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
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it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */
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it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
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/* (3) Exit the configuration state (MB PnP mode). */
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it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
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it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
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}
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@ -20,3 +20,4 @@
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config chip.h
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object superio.o
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@ -19,7 +19,7 @@
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*/
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/* Datasheet: http://www.datasheet4u.com/html/I/T/8/IT8673F_ITE.pdf.html */
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/* Status: untested on real hardware, but it compiles. */
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/* Status: Untested on real hardware, but it compiles. */
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#define IT8673F_FDC 0x00 /* Floppy */
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#define IT8673F_SP1 0x01 /* Com1 */
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA SIO_BASE+1
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/* Global Configuration Registers. */
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/* Global configuration registers. */
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#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8673F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
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#define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */
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/* Special values used for entering MB PnP mode. The first four bytes of
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* each line determine the address port, the last four are data. */
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each line determine the address port, the last four are data. */
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static const uint8_t init_values[] = {
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0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
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0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
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};
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/* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the
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* LDN the register belongs to, before you can access the register. */
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LDN the register belongs to, before you can access the register. */
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static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
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{
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outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
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outb(value, SIO_DATA);
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}
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/* Enable the peripheral devices on the IT8673F Super IO chip. */
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/* Enable the peripheral devices on the IT8673F Super I/O chip. */
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static void it8673f_enable_serial(device_t dev, unsigned iobase)
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{
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uint8_t i;
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it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00);
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/* (3) Exit the configuration state (MB PnP mode). */
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it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02);
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it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02);
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}
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@ -20,3 +20,4 @@
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config chip.h
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object superio.o
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@ -19,7 +19,7 @@
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*/
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/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8705_2.asp */
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/* Status: untested on real hardware, but it compiles. */
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/* Status: Untested on real hardware, but it compiles. */
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/* Note: This should also work on an IT8705AF, they're almost the same. */
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/* This chip doesn't seem to have keyboard and mouse support. */
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@ -26,19 +26,19 @@
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA SIO_BASE+1
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/* Global Configuration Registers. */
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/* Global configuration registers. */
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#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
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/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
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#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection. */
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#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend, Flash I/F. */
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#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */
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#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */
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#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */
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/* The content of IT8705F_CONFIG_REG_LDN (index 0x07) must be set to the
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* LDN the register belongs to, before you can access the register. */
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LDN the register belongs to, before you can access the register. */
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static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
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{
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outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
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outb(value, SIO_DATA);
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}
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/* Enable the peripheral devices on the IT8705F Super IO chip. */
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/* Enable the peripheral devices on the IT8705F Super I/O chip. */
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static void it8705f_enable_serial(device_t dev, unsigned iobase)
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{
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/* (1) Enter the configuration state (MB PnP mode). */
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/* (2) Modify the data of configuration registers. */
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/* Select the chip to configure (if there's more than one).
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* Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
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* If this register is not written, both chips are configured. */
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Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
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If this register is not written, both chips are configured. */
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/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
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/* Enable all devices. */
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@ -73,18 +73,17 @@ static void it8705f_enable_serial(device_t dev, unsigned iobase)
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it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
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it8705f_sio_write(IT8705F_PP, 0x30, 0x1); /* Parallel port */
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it8705f_sio_write(IT8705F_EC, 0x30, 0x1); /* Environment controller */
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/* GPIO */
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it8705f_sio_write(IT8705F_GAME, 0x30, 0x1); /* GAME port */
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it8705f_sio_write(IT8705F_IR, 0x30, 0x1); /* Consumer IR */
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it8705f_sio_write(IT8705F_MIDI, 0x30, 0x1); /* MIDI port */
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/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
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/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x00); */
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/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); */
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/* Clear software suspend mode (clear bit 0). TODO: Needed? */
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/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
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/* (3) Exit the configuration state (MB PnP mode). */
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it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
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it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
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}
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config chip.h
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object superio.o
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*/
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/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */
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/* Status: untested on real hardware, but it compiles. */
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/* Status: Untested on real hardware, but it compiles. */
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#define IT8712F_FDC 0x00 /* Floppy */
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#define IT8712F_SP1 0x01 /* Com1 */
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#define SIO_INDEX SIO_BASE
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#define SIO_DATA SIO_BASE+1
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/* Global Configuration Registers. */
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/* Global configuration registers. */
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#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
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#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
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/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
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* LDN the register belongs to, before you can access the register. */
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LDN the register belongs to, before you can access the register. */
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static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
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{
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outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
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outb(value, SIO_DATA);
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}
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/* Enable the peripheral devices on the IT8712F Super IO chip. */
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/* Enable the peripheral devices on the IT8712F Super I/O chip. */
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static void it8712f_enable_serial(device_t dev, unsigned iobase)
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{
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/* (1) Enter the configuration state (MB PnP mode). */
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@ -61,8 +61,8 @@ static void it8712f_enable_serial(device_t dev, unsigned iobase)
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/* (2) Modify the data of configuration registers. */
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/* Select the chip to configure (if there's more than one).
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* Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
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* If this register is not written, both chips are configured. */
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Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
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If this register is not written, both chips are configured. */
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/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
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/* Enable all devices. */
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it8712f_sio_write(IT8712F_IR, 0x30, 0x1); /* Consumer IR */
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/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
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/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x00); */
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/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); */
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/* Clear software suspend mode (clear bit 0). TODO: Needed? */
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/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
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/* (3) Exit the configuration state (MB PnP mode). */
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it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
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it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,3 +20,4 @@
|
|||
|
||||
config chip.h
|
||||
object superio.o
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
*/
|
||||
|
||||
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */
|
||||
/* Status: untested on real hardware, but it compiles. */
|
||||
/* Status: Untested on real hardware, but it compiles. */
|
||||
|
||||
#define IT8716F_FDC 0x00 /* Floppy */
|
||||
#define IT8716F_SP1 0x01 /* Com1 */
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#define SIO_INDEX SIO_BASE
|
||||
#define SIO_DATA SIO_BASE+1
|
||||
|
||||
/* Global Configuration Registers. */
|
||||
/* Global configuration registers. */
|
||||
#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
|
||||
#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
|
||||
#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
#define IT8716F_CONFIGURATION_PORT 0x2e /* Write-only. */
|
||||
|
||||
/* The content of IT8716F_CONFIG_REG_LDN (index 0x07) must be set to the
|
||||
* LDN the register belongs to, before you can access the register. */
|
||||
LDN the register belongs to, before you can access the register. */
|
||||
static void it8716f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
|
||||
{
|
||||
outb(IT8716F_CONFIG_REG_LDN, SIO_BASE);
|
||||
|
|
@ -45,7 +45,7 @@ static void it8716f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
|
|||
outb(value, SIO_DATA);
|
||||
}
|
||||
|
||||
/* Enable the peripheral devices on the IT8716F Super IO chip. */
|
||||
/* Enable the peripheral devices on the IT8716F Super I/O chip. */
|
||||
static void it8716f_enable_serial(device_t dev, unsigned iobase)
|
||||
{
|
||||
/* (1) Enter the configuration state (MB PnP mode). */
|
||||
|
|
@ -61,8 +61,8 @@ static void it8716f_enable_serial(device_t dev, unsigned iobase)
|
|||
/* (2) Modify the data of configuration registers. */
|
||||
|
||||
/* Select the chip to configure (if there's more than one).
|
||||
* Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
|
||||
* If this register is not written, both chips are configured. */
|
||||
Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
|
||||
If this register is not written, both chips are configured. */
|
||||
/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CONFIGSEL, 0x00); */
|
||||
|
||||
/* Enable all devices. */
|
||||
|
|
@ -78,12 +78,12 @@ static void it8716f_enable_serial(device_t dev, unsigned iobase)
|
|||
it8716f_sio_write(IT8716F_IR, 0x30, 0x1); /* Consumer IR */
|
||||
|
||||
/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
|
||||
/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CLOCKSEL, 0x00); */
|
||||
/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CLOCKSEL, 0x01); */
|
||||
|
||||
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
|
||||
/* it8716f_sio_write(0x00, IT8716F_CONFIG_REG_SWSUSP, 0x00); */
|
||||
|
||||
/* (3) Exit the configuration state (MB PnP mode). */
|
||||
it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CC, 0x02);
|
||||
it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CC, 0x02);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,3 +20,4 @@
|
|||
|
||||
config chip.h
|
||||
object superio.o
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
*/
|
||||
|
||||
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
|
||||
/* Status: untested on real hardware, but it compiles. */
|
||||
/* Status: Untested on real hardware, but it compiles. */
|
||||
|
||||
#define IT8718F_FDC 0x00 /* Floppy */
|
||||
#define IT8718F_SP1 0x01 /* Com1 */
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#define SIO_INDEX SIO_BASE
|
||||
#define SIO_DATA SIO_BASE+1
|
||||
|
||||
/* Global Configuration Registers. */
|
||||
/* Global configuration registers. */
|
||||
#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
|
||||
#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
|
||||
#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
|
||||
|
|
@ -36,7 +36,7 @@
|
|||
#define IT8718F_CONFIGURATION_PORT 0x2e /* Write-only. */
|
||||
|
||||
/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the
|
||||
* LDN the register belongs to, before you can access the register. */
|
||||
LDN the register belongs to, before you can access the register. */
|
||||
static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
|
||||
{
|
||||
outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
|
||||
|
|
@ -45,7 +45,7 @@ static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
|
|||
outb(value, SIO_DATA);
|
||||
}
|
||||
|
||||
/* Enable the peripheral devices on the IT8718F Super IO chip. */
|
||||
/* Enable the peripheral devices on the IT8718F Super I/O chip. */
|
||||
static void it8718f_enable_serial(device_t dev, unsigned iobase)
|
||||
{
|
||||
/* (1) Enter the configuration state (MB PnP mode). */
|
||||
|
|
@ -61,8 +61,8 @@ static void it8718f_enable_serial(device_t dev, unsigned iobase)
|
|||
/* (2) Modify the data of configuration registers. */
|
||||
|
||||
/* Select the chip to configure (if there's more than one).
|
||||
* Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
|
||||
* If this register is not written, both chips are configured. */
|
||||
Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
|
||||
If this register is not written, both chips are configured. */
|
||||
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
|
||||
|
||||
/* Enable all devices. */
|
||||
|
|
@ -76,12 +76,12 @@ static void it8718f_enable_serial(device_t dev, unsigned iobase)
|
|||
it8718f_sio_write(IT8718F_IR, 0x30, 0x1); /* Consumer IR */
|
||||
|
||||
/* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */
|
||||
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x00); */
|
||||
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01); */
|
||||
|
||||
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
|
||||
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
|
||||
|
||||
/* (3) Exit the configuration state (MB PnP mode). */
|
||||
it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
|
||||
it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue