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intel/cannonlake_rvp: enable CNVi wifi 

Leaving the wifi related gpios unmodified for now
due to FSP problem. If H0-H3 is configured as native mode
and GPIORXDIS, GPIOTXDIS bits in DW0 are cleared, it causes
FSP to assert when wifi module is attached. coreboot gpio
macros clears these 2 bits because they are suppose to be
"don't care" in native mode.

TEST=Boot to OS and verify wifi

Change-Id: Ica5e1c43802d04a9471cdfa0087e86f669122fff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bora Guvendik 2017-10-17 16:52:43 -07:00 committed by Aaron Durbin
parent 9a506d5c9a
commit 154cd41037
3 changed files with 2 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
View File

@ -220,13 +220,9 @@ static const struct pad_config gpio_table[] = {
/* F3 : GPP_F_3 */ /* F3 : GPP_F_3 */
PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),
/* F4 : CNV_BRI_DT_UART0_RTSB */ /* F4 : CNV_BRI_DT_UART0_RTSB */
PAD_CFG_NF(GPP_F4, UP_20K, DEEP, GPIO),
/* F5 : CNV_BRI_RSP_UART0_RXD */ /* F5 : CNV_BRI_RSP_UART0_RXD */
PAD_CFG_NF(GPP_F5, UP_20K, DEEP, GPIO),
/* F6 : CNV_RGI_DT_UART0_TXD */ /* F6 : CNV_RGI_DT_UART0_TXD */
PAD_CFG_NF(GPP_F6, UP_20K, DEEP, GPIO),
/* F7 : CNV_RGI_DT_RSP_UART9_CTSB */ /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */
PAD_CFG_NF(GPP_F7, UP_20K, DEEP, GPIO),
/* F8 : CNV_MFUART2_RXD */ /* F8 : CNV_MFUART2_RXD */
PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1), PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1),
/* F9 : CNV_MFUART2_TXD */ /* F9 : CNV_MFUART2_TXD */
@ -266,13 +262,9 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_G7, DN_20K, DEEP, GPIO), PAD_CFG_NF(GPP_G7, DN_20K, DEEP, GPIO),
/* H0 : SSP2_SCLK */ /* H0 : SSP2_SCLK */
PAD_CFG_NF(GPP_H0, UP_20K, DEEP, GPIO),
/* H1 : SSP2_SFRM */ /* H1 : SSP2_SFRM */
PAD_CFG_NF(GPP_H1, UP_20K, DEEP, GPIO),
/* H2 : SSP2_TXD */ /* H2 : SSP2_TXD */
PAD_CFG_NF(GPP_H2, UP_20K, DEEP, GPIO),
/* H3 : SSP2_RXD */ /* H3 : SSP2_RXD */
PAD_CFG_NF(GPP_H3, UP_20K, DEEP, GPIO),
/* H4 : I2C2_SDA */ /* H4 : I2C2_SDA */
/* H5 : I2C2_SCL */ /* H5 : I2C2_SCL */
/* H6 : I2C3_SDA */ /* H6 : I2C3_SDA */

1
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View File

@ -79,6 +79,7 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 14.0 on end # USB xHCI device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on end # CNVi wifi
device pci 14.5 on end # SDCard device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C #0 device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1 device pci 15.1 on end # I2C #1

1
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -77,6 +77,7 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 14.0 on end # USB xHCI device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on end # CNVi wifi
device pci 14.5 on end # SDCard device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C #0 device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1 device pci 15.1 on end # I2C #1