cpu/intel: Enter romstage without BIST

When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.

Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/intel/car/romstage.c

@@ -61,7 +61,7 @@ static void romstage_main(unsigned long bist)
 	for (i = 0; i < num_guards; i++)
 		stack_base[i] = stack_guard;
 
-	mainboard_romstage_entry(bist);
+	mainboard_romstage_entry();
 
 	/* Check the stack. */
 	for (i = 0; i < num_guards; i++) {

src/cpu/intel/haswell/haswell.h

@@ -141,7 +141,6 @@ struct romstage_params {
 	struct pei_data *pei_data;
 	const void *gpio_map;
 	const struct rcba_config_instruction *rcba_config;
-	unsigned long bist;
 	void (*copy_spd)(struct pei_data *);
 };
 void romstage_common(const struct romstage_params *params);

src/cpu/intel/haswell/romstage.c

@@ -33,14 +33,10 @@ void romstage_common(const struct romstage_params *params)
 	int boot_mode;
 	int wake_from_s3;
 
-	if (params->bist == 0)
 	enable_lapic();
 
 	wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(params->bist);
-
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */

src/drivers/intel/fsp1_1/car.c

@@ -37,7 +37,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 }
 
 /* This is the romstage entry called from cpu/intel/car/romstage.c */
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
 	 * is still enabled. We can directly access work buffer here. */

src/include/cpu/intel/romstage.h

@@ -3,7 +3,7 @@
 
 #include <arch/cpu.h>
 
-void mainboard_romstage_entry(unsigned long bist);
+void mainboard_romstage_entry(void);
 
 /* fill_postcar_frame() is called after raminit completes and right before
  * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()

src/mainboard/aopen/dxplplusu/romstage.c

@@ -26,7 +26,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	static const struct mem_controller memctrl[] = {
 		{

src/mainboard/apple/macbook21/romstage.c

@@ -22,7 +22,6 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
@@ -223,12 +222,11 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
 
-	if (bist == 0)
 	enable_lapic();
 
 	ich7_enable_lpc();
@@ -236,9 +234,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG,
 		       "Soft reset detected, rebooting properly.\n");

src/mainboard/asrock/g41c-gs/romstage.c

@@ -19,7 +19,6 @@
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/x86/bist.h>
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>
@@ -82,7 +81,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -95,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/asrock/h81m-hds/romstage.c

@@ -39,7 +39,7 @@ static const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -94,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = &rcba_config[0],
-		.bist = bist,
 	};
 
 	romstage_common(&romstage_params);

src/mainboard/asus/p2b-ds/romstage.c

@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83977tf/w83977tf.h>
@@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	sdram_initialize();

src/mainboard/asus/p2b-ls/romstage.c

@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
@@ -32,11 +31,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	sdram_initialize();

src/mainboard/asus/p2b/romstage.c

@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83977tf/w83977tf.h>
@@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	sdram_initialize();

src/mainboard/asus/p3b-f/romstage.c

@@ -19,7 +19,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
@@ -65,11 +64,10 @@ static void disable_spd(void)
 	outb(0x67, PM_IO_BASE + 0x37);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	enable_pm();

src/mainboard/asus/p5gc-mx/romstage.c

@@ -24,7 +24,6 @@
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -173,13 +172,12 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0, boot_mode = 0;
 
 	u8 c_bsel = msr_get_fsb();
 
-	if (bist == 0)
 	enable_lapic();
 
 	ich7_enable_lpc();
@@ -189,9 +187,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected.\n");
 		boot_mode = 1;

src/mainboard/asus/p5qc/romstage.c

@@ -20,7 +20,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/w83667hg-a/w83667hg-a.h>
 #include <superio/winbond/common/winbond.h>
@@ -66,7 +65,7 @@ static void ich10_enable_lpc(void)
 	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
 	u8 boot_path = 0;
@@ -79,7 +78,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/asus/p5qpl-am/romstage.c

@@ -21,7 +21,6 @@
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/intel/speedstep.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
@@ -162,7 +161,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(LPC_DEV, 0x84, 0x000295);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -176,7 +175,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/foxconn/g41s-k/romstage.c

@@ -17,7 +17,6 @@
  */
 
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <device/pci_ops.h>
 #include <northbridge/intel/x4x/iomap.h>
@@ -81,7 +80,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
 #if CONFIG(BOARD_FOXCONN_G41S_K)
@@ -101,7 +100,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/getac/p470/romstage.c

@@ -24,7 +24,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -232,11 +231,10 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 
-	if (bist == 0)
 	enable_lapic();
 
 #if 0
@@ -252,9 +250,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		system_reset();

src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c

@@ -21,7 +21,6 @@
 #include <superio/ite/it8718f/it8718f.h>
 #include <superio/ite/common/ite.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -135,11 +134,9 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0, boot_mode = 0;
-
-	if (bist == 0)
 	enable_lapic();
 
 	ich7_enable_lpc();
@@ -153,9 +150,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected.\n");
 		boot_mode = 1;

src/mainboard/gigabyte/ga-g41m-es2l/romstage.c

@@ -22,7 +22,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/ite/it8718f/it8718f.h>
 #include <superio/ite/common/ite.h>
@@ -122,7 +121,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -139,7 +138,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/google/beltino/romstage.c

@@ -67,7 +67,7 @@ const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -130,7 +130,6 @@ void mainboard_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = &rcba_config[0],
-		.bist = bist,
 	};
 
 	/* Early SuperIO setup */

src/mainboard/google/slippy/romstage.c

@@ -18,7 +18,7 @@
 #include "variant.h"
 
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
-    variant_romstage_entry(bist);
+	variant_romstage_entry();
 }

src/mainboard/google/slippy/variant.h

@@ -16,6 +16,6 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
-void variant_romstage_entry(unsigned long bist);
+void variant_romstage_entry(void);
 
 #endif

src/mainboard/google/slippy/variants/falco/romstage.c

@@ -105,7 +105,7 @@ static void copy_spd(struct pei_data *peid)
 	}
 }
 
-void variant_romstage_entry(unsigned long bist)
+void variant_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -167,7 +167,6 @@ void variant_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = &rcba_config[0],
-		.bist = bist,
 		.copy_spd = copy_spd,
 	};
 

src/mainboard/google/slippy/variants/leon/romstage.c

@@ -102,7 +102,7 @@ static void copy_spd(struct pei_data *peid)
 			spd_file + (spd_index * spd_len), spd_len);
 }
 
-void variant_romstage_entry(unsigned long bist)
+void variant_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -162,7 +162,6 @@ void variant_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = &rcba_config[0],
-		.bist = bist,
 		.copy_spd = copy_spd,
 	};
 

src/mainboard/google/slippy/variants/peppy/romstage.c

@@ -119,7 +119,7 @@ static void copy_spd(struct pei_data *peid)
 	}
 }
 
-void variant_romstage_entry(unsigned long bist)
+void variant_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -179,7 +179,6 @@ void variant_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = &rcba_config[0],
-		.bist = bist,
 		.copy_spd = copy_spd,
 	};
 

src/mainboard/google/slippy/variants/wolf/romstage.c

@@ -106,7 +106,7 @@ static void copy_spd(struct pei_data *peid)
 	}
 }
 
-void variant_romstage_entry(unsigned long bist)
+void variant_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -166,7 +166,6 @@ void variant_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = &rcba_config[0],
-		.bist = bist,
 		.copy_spd = copy_spd,
 	};
 

src/mainboard/ibase/mb899/romstage.c

@@ -19,7 +19,6 @@
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
@@ -197,11 +196,10 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 
-	if (bist == 0)
 	enable_lapic();
 
 	ich7_enable_lpc();
@@ -210,9 +208,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		system_reset();

src/mainboard/intel/baskingridge/romstage.c

@@ -63,7 +63,7 @@ const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -136,7 +136,6 @@ void mainboard_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = &rcba_config[0],
-		.bist = bist,
 		.copy_spd = NULL,
 	};
 

src/mainboard/intel/d945gclf/romstage.c

@@ -19,7 +19,6 @@
 #include <cpu/x86/lapic.h>
 #include <superio/smsc/lpc47m15x/lpc47m15x.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -117,11 +116,10 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0, boot_mode = 0;
 
-	if (bist == 0)
 	enable_lapic();
 
 	ich7_enable_lpc();
@@ -132,9 +130,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected.\n");
 		boot_mode = 1;

src/mainboard/intel/dg41wv/romstage.c

@@ -19,7 +19,6 @@
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/x86/bist.h>
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <southbridge/intel/common/gpio.h>
@@ -75,7 +74,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -89,7 +88,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/intel/dg43gt/romstage.c

@@ -20,7 +20,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
 #include <superio/winbond/common/winbond.h>
@@ -68,7 +67,7 @@ static void ich10_enable_lpc(void)
 	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
 	u8 boot_path = 0;
@@ -81,7 +80,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/kontron/986lcd-m/romstage.c

@@ -18,7 +18,6 @@
 #include <delay.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
@@ -241,11 +240,10 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 
-	if (bist == 0)
 	enable_lapic();
 
 	/* Force PCIRST# */
@@ -259,9 +257,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		system_reset();

src/mainboard/lenovo/t60/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -157,13 +156,12 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 	int dock_err;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-	if (bist == 0)
 	enable_lapic();
 
 	ich7_enable_lpc();
@@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Setup the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		system_reset();

src/mainboard/lenovo/thinkcentre_a58/romstage.c

@@ -20,7 +20,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <device/pci_ops.h>
 #include <superio/smsc/smscsuperio/smscsuperio.h>
@@ -60,7 +59,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -74,7 +73,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();

src/mainboard/lenovo/x201/romstage.c

@@ -23,7 +23,6 @@
 #include <cpu/x86/lapic.h>
 #include <romstage_handoff.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <ec/acpi/ec.h>
 #include <timestamp.h>
@@ -167,13 +166,11 @@ static void set_fsb_frequency(void)
 	smbus_block_write(0x69, 0, 5, block);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	u32 reg32;
 	int s3resume = 0;
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
-
-	if (bist == 0)
 	enable_lapic();
 
 	nehalem_early_initialization(NEHALEM_MOBILE);
@@ -197,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	/* Read PM1_CNT */
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);

src/mainboard/lenovo/x60/romstage.c

@@ -25,7 +25,6 @@
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -157,12 +156,11 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-	if (bist == 0)
 	enable_lapic();
 
 	/* Enable GPIOs */
@@ -190,9 +188,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	else
 		printk(BIOS_DEBUG, "Dock is not present\n");
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG,
 		       "Soft reset detected, rebooting properly.\n");

src/mainboard/lenovo/z61t/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -157,13 +156,12 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 	int dock_err;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-	if (bist == 0)
 	enable_lapic();
 
 	ich7_enable_lpc();
@@ -188,9 +186,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Setup the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		system_reset();

src/mainboard/packardbell/ms2290/romstage.c

@@ -23,7 +23,6 @@
 #include <cpu/x86/lapic.h>
 #include <romstage_handoff.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <ec/acpi/ec.h>
 #include <timestamp.h>
@@ -159,7 +158,7 @@ static inline u16 read_acpi16(u32 addr)
 }
 #endif
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	u32 reg32;
 	int s3resume = 0;
@@ -169,7 +168,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	outb(4, 0x61);
 	outb(0, 0x61);
 
-	if (bist == 0)
 	enable_lapic();
 
 	nehalem_early_initialization(NEHALEM_MOBILE);
@@ -196,9 +194,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	/* Read PM1_CNT */
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);

src/mainboard/roda/rk886ex/romstage.c

@@ -24,7 +24,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -204,11 +203,10 @@ static void init_artec_dongle(void)
 	outb(0xf4, 0x88);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 
-	if (bist == 0)
 	enable_lapic();
 
 	/* Force PCIRST# */
@@ -222,9 +220,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 		system_reset();

src/mainboard/supermicro/x10slm-f/romstage.c

@@ -38,7 +38,7 @@ static const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -92,7 +92,6 @@ void mainboard_romstage_entry(unsigned long bist)
 		.pei_data = &pei_data,
 		.gpio_map = &mainboard_gpio_map,
 		.rcba_config = rcba_config,
-		.bist = bist,
 	};
 
 	romstage_common(&romstage_params);

src/northbridge/intel/gm45/romstage.c

@@ -21,7 +21,6 @@
 #include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
@@ -47,7 +46,7 @@ void __weak mb_post_raminit_setup(void)
 /* Platform has no romstage entry point under mainboard directory,
  * so this one is named with prefix mainboard.
  */
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	sysinfo_t sysinfo;
 	int s3resume = 0;
@@ -57,7 +56,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
-	if (bist == 0)
 	enable_lapic();
 
 	/* First, run everything needed for console output. */
@@ -69,7 +67,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	mb_setup_superio();
 
 	console_init();
-	report_bist_failure(bist);
 
 	reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
 	pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);

src/northbridge/intel/pineview/romstage.c

@@ -27,7 +27,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <cpu/intel/romstage.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
 #include "raminit.h"
 #include "pineview.h"
@@ -48,13 +47,12 @@ __weak void mb_pirq_setup(void)
 
 #define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0)
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	u8 spd_addrmap[4] = {};
 	int boot_path, cbmem_was_initted;
 	int s3resume = 0;
 
-	if (bist == 0)
 	enable_lapic();
 
 	/* Enable GPIOs */
@@ -63,9 +61,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	setup_pch_gpios(&mainboard_gpio_map);
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	enable_smbus();
 
 	/* Perform some early chipset initialization required

src/northbridge/intel/sandybridge/romstage.c

@@ -22,7 +22,6 @@
 #include <cpu/x86/lapic.h>
 #include <timestamp.h>
 #include "sandybridge.h"
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <device/pci_def.h>
 #include <device/device.h>
@@ -44,14 +43,13 @@ static void early_pch_reset_pmcon(void)
 /* Platform has no romstage entry point under mainboard directory,
  * so this one is named with prefix mainboard.
  */
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0;
 
 	if (MCHBAR16(SSKPD) == 0xCAFE)
 		system_reset();
 
-	if (bist == 0)
 	enable_lapic();
 
 	/* Init LPC, GPIO, BARs, disable watchdog ... */
@@ -68,9 +66,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Initialize console device(s) */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */

src/soc/intel/baytrail/include/soc/romstage.h

@@ -25,7 +25,6 @@
 #include <soc/mrc_wrapper.h>
 
 struct romstage_params {
-	unsigned long bist;
 	struct mrc_params *mrc_params;
 };
 

src/soc/intel/baytrail/romstage/romstage.c

@@ -115,10 +115,9 @@ static void spi_init(void)
 }
 
 /* Entry from cache-as-ram.inc. */
-static void romstage_main(uint64_t tsc, uint32_t bist)
+static void romstage_main(uint64_t tsc)
 {
 	struct romstage_params rp = {
-		.bist = bist,
 		.mrc_params = NULL,
 	};
 
@@ -159,7 +158,7 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
  */
 asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
 {
-	romstage_main(base_timestamp, bist);
+	romstage_main(base_timestamp);
 }
 
 static struct chipset_power_state power_state;

src/soc/intel/broadwell/romstage/romstage.c

@@ -49,7 +49,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 }
 
 /* Entry from cpu/intel/car/romstage.c. */
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	struct romstage_params rp = { 0 };